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author | Diana Picus <diana.picus@linaro.org> | 2017-02-28 12:13:58 +0000 |
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committer | Diana Picus <diana.picus@linaro.org> | 2017-02-28 12:13:58 +0000 |
commit | 5b8514559ed060aef2cfea716ce47547c3b46d4a (patch) | |
tree | 925c99e12fae571ea7f244cb4e4acbf55c0a6808 | |
parent | e6beac674235dda4dae3e25eee51a36518d44069 (diff) | |
download | bcm5719-llvm-5b8514559ed060aef2cfea716ce47547c3b46d4a.tar.gz bcm5719-llvm-5b8514559ed060aef2cfea716ce47547c3b46d4a.zip |
[ARM] GlobalISel: Add mapping for G_CONSTANT
Like G_FRAME_INDEX, G_CONSTANT has one register operand and one non-register
operand.
llvm-svn: 296469
-rw-r--r-- | llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp | 1 | ||||
-rw-r--r-- | llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir | 18 |
2 files changed, 19 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp index 2d512428d6e..18ce7d454b8 100644 --- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp +++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp @@ -240,6 +240,7 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { ? &ARM::ValueMappings[ARM::DPR3OpsIdx] : &ARM::ValueMappings[ARM::SPR3OpsIdx]; break; + case G_CONSTANT: case G_FRAME_INDEX: OperandsMapping = getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr}); diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir index 5b54ead6a63..355d723a3e7 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir @@ -10,6 +10,8 @@ define void @test_gep() { ret void } + define void @test_constants() { ret void } + define void @test_fadd_s32() #0 { ret void } define void @test_fadd_s64() #0 { ret void } @@ -225,6 +227,22 @@ body: | BX_RET 14, _, implicit %r0 ... --- +name: test_constants +# CHECK-LABEL: name: test_constants +legalized: true +regBankSelected: false +selected: false +# CHECK: registers: +# CHECK: - { id: 0, class: gprb } +registers: + - { id: 0, class: _ } +body: | + bb.0: + %0(s32) = G_CONSTANT 42 + %r0 = COPY %0(s32) + BX_RET 14, _, implicit %r0 +... +--- name: test_fadd_s32 # CHECK-LABEL: name: test_fadd_s32 legalized: true |