[AArch64][SVE] Asm: Support for contiguous LD1 (scalar+imm) load instructions

Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro

Reviewed By: rengolin

Subscribers: tschuett, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D45618

llvm-svn: 330024

17 files changed, 975 insertions, 0 deletions

diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
index 09d0a753072..a4e9b4426d6 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
@@ -131,6 +131,9 @@ def XZR   : AArch64Reg<31, "xzr", [WZR]>, DwarfRegAlias<WSP>;
 // Condition code register.
 def NZCV  : AArch64Reg<0, "nzcv">;
 
+// First fault status register
+def FFR : AArch64Reg<0, "ffr">, DwarfRegNum<[47]>;
+
 // GPR register classes with the intersections of GPR32/GPR32sp and
 // GPR64/GPR64sp for use by the coalescer.
 def GPR32common : RegisterClass<"AArch64", [i32], 32, (sequence "W%u", 0, 30)> {
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 6a13003ab02..b3bed53762d 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -20,6 +20,23 @@ let Predicates = [HasSVE] in {
   defm ADD_ZPmZ  : sve_int_bin_pred_arit_0<0b000, "add">;
   defm SUB_ZPmZ  : sve_int_bin_pred_arit_0<0b001, "sub">;
 
+  // continuous load with reg+immediate
+  defm LD1B_IMM    : sve_mem_cld_si<0b0000, "ld1b",  Z_b, ZPR8>;
+  defm LD1B_H_IMM  : sve_mem_cld_si<0b0001, "ld1b",  Z_h, ZPR16>;
+  defm LD1B_S_IMM  : sve_mem_cld_si<0b0010, "ld1b",  Z_s, ZPR32>;
+  defm LD1B_D_IMM  : sve_mem_cld_si<0b0011, "ld1b",  Z_d, ZPR64>;
+  defm LD1SW_D_IMM : sve_mem_cld_si<0b0100, "ld1sw", Z_d, ZPR64>;
+  defm LD1H_IMM    : sve_mem_cld_si<0b0101, "ld1h",  Z_h, ZPR16>;
+  defm LD1H_S_IMM  : sve_mem_cld_si<0b0110, "ld1h",  Z_s, ZPR32>;
+  defm LD1H_D_IMM  : sve_mem_cld_si<0b0111, "ld1h",  Z_d, ZPR64>;
+  defm LD1SH_D_IMM : sve_mem_cld_si<0b1000, "ld1sh", Z_d, ZPR64>;
+  defm LD1SH_S_IMM : sve_mem_cld_si<0b1001, "ld1sh", Z_s, ZPR32>;
+  defm LD1W_IMM    : sve_mem_cld_si<0b1010, "ld1w",  Z_s, ZPR32>;
+  defm LD1W_D_IMM  : sve_mem_cld_si<0b1011, "ld1w",  Z_d, ZPR64>;
+  defm LD1SB_D_IMM : sve_mem_cld_si<0b1100, "ld1sb", Z_d, ZPR64>;
+  defm LD1SB_S_IMM : sve_mem_cld_si<0b1101, "ld1sb", Z_s, ZPR32>;
+  defm LD1SB_H_IMM : sve_mem_cld_si<0b1110, "ld1sb", Z_h, ZPR16>;
+  defm LD1D_IMM    : sve_mem_cld_si<0b1111, "ld1d",  Z_d, ZPR64>;
 
   // continuous store with immediates
   defm ST1B_IMM   : sve_mem_cst_si<0b00, 0b00, "st1b", Z_b, ZPR8>;
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index 73e79559e7c..95af6682941 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -575,3 +575,47 @@ multiclass sve_int_perm_bin_perm_pp<bits<3> opc, string asm> {
   def _S : sve_int_perm_bin_perm_pp<opc, 0b10, asm, PPR32>;
   def _D : sve_int_perm_bin_perm_pp<opc, 0b11, asm, PPR64>;
 }
+
+//===----------------------------------------------------------------------===//
+// SVE Memory - Contiguous Load Group
+//===----------------------------------------------------------------------===//
+
+class sve_mem_cld_si_base<bits<4> dtype, bit nf, string asm,
+                          RegisterOperand VecList>
+: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4MulVl:$imm4),
+  asm, "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",
+  "",
+  []>, Sched<[]> {
+  bits<3> Pg;
+  bits<5> Rn;
+  bits<5> Zt;
+  bits<4> imm4;
+  let Inst{31-25} = 0b1010010;
+  let Inst{24-21} = dtype;
+  let Inst{20}    = nf;
+  let Inst{19-16} = imm4;
+  let Inst{15-13} = 0b101;
+  let Inst{12-10} = Pg;
+  let Inst{9-5}   = Rn;
+  let Inst{4-0}   = Zt;
+
+  let mayLoad = 1;
+  let Uses = !if(!eq(nf, 1), [FFR], []);
+  let Defs = !if(!eq(nf, 1), [FFR], []);
+}
+
+multiclass sve_mem_cld_si_base<bits<4> dtype, bit nf, string asm,
+                               RegisterOperand listty, ZPRRegOp zprty> {
+  def _REAL : sve_mem_cld_si_base<dtype, nf, asm, listty>;
+
+  def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
+                  (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
+  def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",
+                  (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4MulVl:$imm4), 0>;
+  def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
+                  (!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
+}
+
+multiclass sve_mem_cld_si<bits<4> dtype, string asm, RegisterOperand listty,
+                          ZPRRegOp zprty>
+: sve_mem_cld_si_base<dtype, 0, asm, listty, zprty>;
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SVE/ld1b-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1b-diagnostics.s
new file mode 100644
index 00000000000..bebc273e65b
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/ld1b-diagnostics.s
@@ -0,0 +1,87 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-8, 7].
+
+ld1b z23.b, p0/z, [x13, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1b z23.b, p0/z, [x13, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b z29.b, p0/z, [x3, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1b z29.b, p0/z, [x3, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b z21.h, p4/z, [x17, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1b z21.h, p4/z, [x17, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b z10.h, p5/z, [x16, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1b z10.h, p5/z, [x16, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b z30.s, p6/z, [x25, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1b z30.s, p6/z, [x25, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b z29.s, p5/z, [x15, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1b z29.s, p5/z, [x15, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1b z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1b z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+ld1b z27.b, p8/z, [x29, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1b z27.b, p8/z, [x29, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b z9.h, p8/z, [x25, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1b z9.h, p8/z, [x25, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b z12.s, p8/z, [x13, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1b z12.s, p8/z, [x13, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1b z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+ld1b { }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: ld1b { }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b { z1.b, z2.b }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1b { z1.b, z2.b }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1b { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/ld1b.s b/llvm/test/MC/AArch64/SVE/ld1b.s
new file mode 100644
index 00000000000..3f31e1e94e6
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/ld1b.s
@@ -0,0 +1,104 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ld1b     z0.b, p0/z, [x0]
+// CHECK-INST: ld1b     { z0.b }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x00,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 00 a4 <unknown>
+
+ld1b     z0.h, p0/z, [x0]
+// CHECK-INST: ld1b     { z0.h }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x20,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 20 a4 <unknown>
+
+ld1b     z0.s, p0/z, [x0]
+// CHECK-INST: ld1b     { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x40,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 40 a4 <unknown>
+
+ld1b     z0.d, p0/z, [x0]
+// CHECK-INST: ld1b     { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x60,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 60 a4 <unknown>
+
+ld1b    { z0.b }, p0/z, [x0]
+// CHECK-INST: ld1b    { z0.b }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x00,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 00 a4 <unknown>
+
+ld1b    { z0.h }, p0/z, [x0]
+// CHECK-INST: ld1b    { z0.h }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x20,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 20 a4 <unknown>
+
+ld1b    { z0.s }, p0/z, [x0]
+// CHECK-INST: ld1b    { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x40,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 40 a4 <unknown>
+
+ld1b    { z0.d }, p0/z, [x0]
+// CHECK-INST: ld1b    { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x60,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 60 a4 <unknown>
+
+ld1b    { z31.b }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ld1b    { z31.b }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0x0f,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 0f a4 <unknown>
+
+ld1b    { z21.b }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ld1b    { z21.b }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x05,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 05 a4 <unknown>
+
+ld1b    { z31.h }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ld1b    { z31.h }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0x2f,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 2f a4 <unknown>
+
+ld1b    { z21.h }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ld1b    { z21.h }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x25,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 25 a4 <unknown>
+
+ld1b    { z31.s }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ld1b    { z31.s }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0x4f,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 4f a4 <unknown>
+
+ld1b    { z21.s }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ld1b    { z21.s }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x45,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 45 a4 <unknown>
+
+ld1b    { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ld1b    { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0x6f,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 6f a4 <unknown>
+
+ld1b    { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ld1b    { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x65,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 65 a4 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/ld1d-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1d-diagnostics.s
new file mode 100644
index 00000000000..2c2ebfa7ac8
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/ld1d-diagnostics.s
@@ -0,0 +1,42 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-8, 7].
+
+ld1d z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1d z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1d z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+ld1d z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1d z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+ld1d { }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: ld1d { }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d { z1.d, z2.d }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1d { z1.d, z2.d }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1d { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/ld1d.s b/llvm/test/MC/AArch64/SVE/ld1d.s
new file mode 100644
index 00000000000..f9b84eaf7c1
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/ld1d.s
@@ -0,0 +1,32 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ld1d     z0.d, p0/z, [x0]
+// CHECK-INST: ld1d     { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xe0,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 e0 a5 <unknown>
+
+ld1d    { z0.d }, p0/z, [x0]
+// CHECK-INST: ld1d    { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xe0,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 e0 a5 <unknown>
+
+ld1d    { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ld1d    { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0xef,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf ef a5 <unknown>
+
+ld1d    { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ld1d    { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0xe5,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 e5 a5 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/ld1h-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1h-diagnostics.s
new file mode 100644
index 00000000000..fb5150ec2af
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/ld1h-diagnostics.s
@@ -0,0 +1,72 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-8, 7].
+
+ld1h z21.h, p4/z, [x17, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1h z21.h, p4/z, [x17, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z10.h, p5/z, [x16, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1h z10.h, p5/z, [x16, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z30.s, p6/z, [x25, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1h z30.s, p6/z, [x25, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z29.s, p5/z, [x15, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1h z29.s, p5/z, [x15, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1h z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1h z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+ld1h z9.h, p8/z, [x25, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1h z9.h, p8/z, [x25, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z12.s, p8/z, [x13, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1h z12.s, p8/z, [x13, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1h z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+ld1h { }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: ld1h { }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h { z1.h, z2.h }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1h { z1.h, z2.h }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1h { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/ld1h.s b/llvm/test/MC/AArch64/SVE/ld1h.s
new file mode 100644
index 00000000000..715dfc26f5c
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/ld1h.s
@@ -0,0 +1,80 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ld1h     z0.h, p0/z, [x0]
+// CHECK-INST: ld1h     { z0.h }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xa0,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 a0 a4 <unknown>
+
+ld1h     z0.s, p0/z, [x0]
+// CHECK-INST: ld1h     { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xc0,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 c0 a4 <unknown>
+
+ld1h     z0.d, p0/z, [x0]
+// CHECK-INST: ld1h     { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xe0,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 e0 a4 <unknown>
+
+ld1h    { z0.h }, p0/z, [x0]
+// CHECK-INST: ld1h    { z0.h }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xa0,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 a0 a4 <unknown>
+
+ld1h    { z0.s }, p0/z, [x0]
+// CHECK-INST: ld1h    { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xc0,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 c0 a4 <unknown>
+
+ld1h    { z0.d }, p0/z, [x0]
+// CHECK-INST: ld1h    { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xe0,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 e0 a4 <unknown>
+
+ld1h    { z31.h }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ld1h    { z31.h }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0xaf,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf af a4 <unknown>
+
+ld1h    { z21.h }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ld1h    { z21.h }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0xa5,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 a5 a4 <unknown>
+
+ld1h    { z31.s }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ld1h    { z31.s }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0xcf,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf cf a4 <unknown>
+
+ld1h    { z21.s }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ld1h    { z21.s }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0xc5,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 c5 a4 <unknown>
+
+ld1h    { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ld1h    { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0xef,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf ef a4 <unknown>
+
+ld1h    { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ld1h    { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0xe5,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 e5 a4 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/ld1sb-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1sb-diagnostics.s
new file mode 100644
index 00000000000..b41bed678a2
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/ld1sb-diagnostics.s
@@ -0,0 +1,86 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid operand (.b)
+
+ld1sb z23.b, p0/z, [x13, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1sb z23.b, p0/z, [x13, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sb z29.b, p0/z, [x3, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1sb z29.b, p0/z, [x3, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-8, 7].
+
+ld1sb z21.h, p4/z, [x17, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sb z21.h, p4/z, [x17, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sb z10.h, p5/z, [x16, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sb z10.h, p5/z, [x16, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sb z30.s, p6/z, [x25, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sb z30.s, p6/z, [x25, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sb z29.s, p5/z, [x15, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sb z29.s, p5/z, [x15, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sb z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sb z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sb z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sb z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+ld1sb z9.h, p8/z, [x25, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1sb z9.h, p8/z, [x25, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sb z12.s, p8/z, [x13, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1sb z12.s, p8/z, [x13, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sb z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1sb z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+ld1sb { }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: ld1sb { }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sb { z1.h, z2.h }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1sb { z1.h, z2.h }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sb { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1sb { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/ld1sb.s b/llvm/test/MC/AArch64/SVE/ld1sb.s
new file mode 100644
index 00000000000..1bd9f700074
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/ld1sb.s
@@ -0,0 +1,80 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ld1sb   z0.h, p0/z, [x0]
+// CHECK-INST: ld1sb   { z0.h }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xc0,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 c0 a5 <unknown>
+
+ld1sb   z0.s, p0/z, [x0]
+// CHECK-INST: ld1sb   { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xa0,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 a0 a5 <unknown>
+
+ld1sb   z0.d, p0/z, [x0]
+// CHECK-INST: ld1sb   { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x80,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 80 a5 <unknown>
+
+ld1sb   { z0.h }, p0/z, [x0]
+// CHECK-INST: ld1sb   { z0.h }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xc0,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 c0 a5 <unknown>
+
+ld1sb   { z0.s }, p0/z, [x0]
+// CHECK-INST: ld1sb   { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xa0,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 a0 a5 <unknown>
+
+ld1sb   { z0.d }, p0/z, [x0]
+// CHECK-INST: ld1sb   { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x80,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 80 a5 <unknown>
+
+ld1sb   { z31.h }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ld1sb   { z31.h }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0xcf,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf cf a5 <unknown>
+
+ld1sb   { z21.h }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ld1sb   { z21.h }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0xc5,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 c5 a5 <unknown>
+
+ld1sb   { z31.s }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ld1sb   { z31.s }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0xaf,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf af a5 <unknown>
+
+ld1sb   { z21.s }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ld1sb   { z21.s }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0xa5,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 a5 a5 <unknown>
+
+ld1sb   { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ld1sb   { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0x8f,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 8f a5 <unknown>
+
+ld1sb   { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ld1sb   { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x85,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 85 a5 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/ld1sh-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1sh-diagnostics.s
new file mode 100644
index 00000000000..27871813a3f
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/ld1sh-diagnostics.s
@@ -0,0 +1,71 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid operand (.h)
+
+ld1sh z23.h, p0/z, [x13, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1sh z23.h, p0/z, [x13, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh z29.h, p0/z, [x3, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1sh z29.h, p0/z, [x3, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-8, 7].
+
+ld1sh z30.s, p6/z, [x25, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sh z30.s, p6/z, [x25, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh z29.s, p5/z, [x15, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sh z29.s, p5/z, [x15, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sh z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sh z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+ld1sh z12.s, p8/z, [x13, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1sh z12.s, p8/z, [x13, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1sh z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+ld1sh { }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: ld1sh { }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh { z1.s, z2.s }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1sh { z1.s, z2.s }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1sh { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/ld1sh.s b/llvm/test/MC/AArch64/SVE/ld1sh.s
new file mode 100644
index 00000000000..b752d84b092
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/ld1sh.s
@@ -0,0 +1,56 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ld1sh   z0.s, p0/z, [x0]
+// CHECK-INST: ld1sh   { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x20,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 20 a5 <unknown>
+
+ld1sh   z0.d, p0/z, [x0]
+// CHECK-INST: ld1sh   { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x00,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 00 a5 <unknown>
+
+ld1sh   { z0.s }, p0/z, [x0]
+// CHECK-INST: ld1sh   { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x20,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 20 a5 <unknown>
+
+ld1sh   { z0.d }, p0/z, [x0]
+// CHECK-INST: ld1sh   { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x00,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 00 a5 <unknown>
+
+ld1sh   { z31.s }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ld1sh   { z31.s }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0x2f,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 2f a5 <unknown>
+
+ld1sh   { z21.s }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ld1sh   { z21.s }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x25,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 25 a5 <unknown>
+
+ld1sh   { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ld1sh   { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0x0f,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 0f a5 <unknown>
+
+ld1sh   { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ld1sh   { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x05,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 05 a5 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/ld1sw-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1sw-diagnostics.s
new file mode 100644
index 00000000000..1c6a942d565
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/ld1sw-diagnostics.s
@@ -0,0 +1,56 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid operand (.s)
+
+ld1sw z23.s, p0/z, [x13, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1sw z23.s, p0/z, [x13, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sw z29.s, p0/z, [x3, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1sw z29.s, p0/z, [x3, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-8, 7].
+
+ld1sw z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sw z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sw z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sw z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+ld1sw z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1sw z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+ld1sw { }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: ld1sw { }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sw { z1.d, z2.d }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1sw { z1.d, z2.d }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sw { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1sw { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/ld1sw.s b/llvm/test/MC/AArch64/SVE/ld1sw.s
new file mode 100644
index 00000000000..58e00721028
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/ld1sw.s
@@ -0,0 +1,32 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ld1sw   z0.d, p0/z, [x0]
+// CHECK-INST: ld1sw   { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x80,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 80 a4 <unknown>
+
+ld1sw   { z0.d }, p0/z, [x0]
+// CHECK-INST: ld1sw   { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x80,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 80 a4 <unknown>
+
+ld1sw   { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ld1sw   { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0x8f,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 8f a4 <unknown>
+
+ld1sw   { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ld1sw   { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x85,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 85 a4 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/ld1w-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1w-diagnostics.s
new file mode 100644
index 00000000000..dc46044948b
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/ld1w-diagnostics.s
@@ -0,0 +1,57 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-8, 7].
+
+ld1w z30.s, p6/z, [x25, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1w z30.s, p6/z, [x25, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w z29.s, p5/z, [x15, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1w z29.s, p5/z, [x15, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1w z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1w z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+ld1w z12.s, p8/z, [x13, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1w z12.s, p8/z, [x13, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1w z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+ld1w { }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: ld1w { }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w { z1.s, z2.s }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1w { z1.s, z2.s }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1w { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/ld1w.s b/llvm/test/MC/AArch64/SVE/ld1w.s
new file mode 100644
index 00000000000..bfb93979db9
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/ld1w.s
@@ -0,0 +1,56 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ld1w     z0.s, p0/z, [x0]
+// CHECK-INST: ld1w     { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x40,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 40 a5 <unknown>
+
+ld1w     z0.d, p0/z, [x0]
+// CHECK-INST: ld1w     { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x60,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 60 a5 <unknown>
+
+ld1w    { z0.s }, p0/z, [x0]
+// CHECK-INST: ld1w    { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x40,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 40 a5 <unknown>
+
+ld1w    { z0.d }, p0/z, [x0]
+// CHECK-INST: ld1w    { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x60,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 60 a5 <unknown>
+
+ld1w    { z31.s }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ld1w    { z31.s }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0x4f,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 4f a5 <unknown>
+
+ld1w    { z21.s }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ld1w    { z21.s }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x45,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 45 a5 <unknown>
+
+ld1w    { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ld1w    { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0x6f,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 6f a5 <unknown>
+
+ld1w    { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ld1w    { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x65,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 65 a5 <unknown>