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author | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2014-05-16 12:27:19 +0000 |
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committer | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2014-05-16 12:27:19 +0000 |
commit | 5a8c1e29007b98f26437a110020e7f27a3a5ac6c (patch) | |
tree | e43900923e0237bbcdd1f7320f43431864080ae9 | |
parent | 948366ac0b81af5a92c99ab4e09088cf865a7c69 (diff) | |
download | bcm5719-llvm-5a8c1e29007b98f26437a110020e7f27a3a5ac6c.tar.gz bcm5719-llvm-5a8c1e29007b98f26437a110020e7f27a3a5ac6c.zip |
[mips][mips64r6] Add Compact zero-compare branch-and-link instructions
Differential Revision: http://reviews.llvm.org/D3718
llvm-svn: 208977
-rw-r--r-- | llvm/lib/Target/Mips/Mips32r6InstrInfo.td | 43 | ||||
-rw-r--r-- | llvm/test/MC/Mips/mips32r6/valid.s | 6 | ||||
-rw-r--r-- | llvm/test/MC/Mips/mips64r6/valid.s | 6 |
3 files changed, 49 insertions, 6 deletions
diff --git a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td index f37fd30461e..aa44964aa30 100644 --- a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td @@ -81,18 +81,24 @@ class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>; class BALC_ENC : BRANCH_OFF26_FM<0b111010>; class BC_ENC : BRANCH_OFF26_FM<0b110010>; class BEQC_ENC : CMP_BRANCH_OFF16_FM<0b001000>; +class BEQZALC_ENC : CMP_BRANCH_RT_OFF16_FM<0b001000>; class BNEC_ENC : CMP_BRANCH_OFF16_FM<0b011000>; +class BNEZALC_ENC : CMP_BRANCH_RT_OFF16_FM<0b011000>; class BLTZC_ENC : CMP_BRANCH_OFF16_FM<0b010111>; class BGEZC_ENC : CMP_BRANCH_OFF16_FM<0b010110>; +class BGTZALC_ENC : CMP_BRANCH_RT_OFF16_FM<0b000111>; class BLEZC_ENC : CMP_BRANCH_RT_OFF16_FM<0b010110>; +class BLTZALC_ENC : CMP_BRANCH_OFF16_FM<0b000111>; class BGTZC_ENC : CMP_BRANCH_RT_OFF16_FM<0b010111>; class BEQZC_ENC : CMP_BRANCH_OFF21_FM<0b110110>; +class BGEZALC_ENC : CMP_BRANCH_OFF16_FM<0b000110>; class BNEZC_ENC : CMP_BRANCH_OFF21_FM<0b111110>; class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>; +class BLEZALC_ENC : CMP_BRANCH_RT_OFF16_FM<0b000110>; class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>; class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>; class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>; @@ -325,6 +331,31 @@ class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd>; class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd>; class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd>; +class BEQZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"beqzalc", brtarget, GPR32Opnd> { + list<Register> Defs = [RA]; +} + +class BGEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezalc", brtarget, GPR32Opnd> { + string Constraints = "$rs = $rt"; + list<Register> Defs = [RA]; +} + +class BGTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzalc", brtarget, GPR32Opnd> { + list<Register> Defs = [RA]; +} + +class BLEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezalc", brtarget, GPR32Opnd> { + list<Register> Defs = [RA]; +} + +class BLTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzalc", brtarget, GPR32Opnd> { + string Constraints = "$rs = $rt"; + list<Register> Defs = [RA]; +} + +class BNEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bnezalc", brtarget, GPR32Opnd> { + list<Register> Defs = [RA]; +} class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { dag OutOperandList = (outs GPROpnd:$rd); dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt); @@ -412,23 +443,23 @@ def BC2EQZ; def BC2NEZ; def BC : BC_ENC, BC_DESC, ISA_MIPS32R6; def BEQC : BEQC_ENC, BEQC_DESC, ISA_MIPS32R6; -def BEQZALC; +def BEQZALC : BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6; def BEQZC : BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6; def BGEC; // Also aliased to blec with operands swapped def BGEUC; // Also aliased to bleuc with operands swapped -def BGEZALC; +def BGEZALC : BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6; def BGEZC : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6; -def BGTZALC; +def BGTZALC : BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6; def BGTZC : BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6; def BITSWAP : BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6; -def BLEZALC; +def BLEZALC : BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6; def BLEZC : BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6; def BLTC; // Also aliased to bgtc with operands swapped def BLTUC; // Also aliased to bgtuc with operands swapped -def BLTZALC; +def BLTZALC : BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6; def BLTZC : BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6; def BNEC : BNEC_ENC, BNEC_DESC, ISA_MIPS32R6; -def BNEZALC; +def BNEZALC : BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6; def BNEZC : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6; def BNVC; def BOVC; diff --git a/llvm/test/MC/Mips/mips32r6/valid.s b/llvm/test/MC/Mips/mips32r6/valid.s index 6f94ad3cc14..7967b0cb170 100644 --- a/llvm/test/MC/Mips/mips32r6/valid.s +++ b/llvm/test/MC/Mips/mips32r6/valid.s @@ -12,14 +12,20 @@ balc 14572256 # CHECK: balc 14572256 # encoding: [0xe8,0x37,0x96,0xb8] bc 14572256 # CHECK: bc 14572256 # encoding: [0xc8,0x37,0x96,0xb8] beqc $5, $6, 256 # CHECK: beqc $5, $6, 256 # encoding: [0x20,0xa6,0x00,0x40] + beqzalc $2, 1332 # CHECK: beqzalc $2, 1332 # encoding: [0x20,0x02,0x01,0x4d] bnec $5, $6, 256 # CHECK: bnec $5, $6, 256 # encoding: [0x60,0xa6,0x00,0x40] + bnezalc $2, 1332 # CHECK: bnezalc $2, 1332 # encoding: [0x60,0x02,0x01,0x4d] beqzc $5, 72256 # CHECK: beqzc $5, 72256 # encoding: [0xd8,0xa0,0x46,0x90] + bgezalc $2, 1332 # CHECK: bgezalc $2, 1332 # encoding: [0x18,0x42,0x01,0x4d] bnezc $5, 72256 # CHECK: bnezc $5, 72256 # encoding: [0xf8,0xa0,0x46,0x90] bltzc $5, 256 # CHECK: bltzc $5, 256 # encoding: [0x5c,0xa5,0x00,0x40] bgezc $5, 256 # CHECK: bgezc $5, 256 # encoding: [0x58,0xa5,0x00,0x40] + bgtzalc $2, 1332 # CHECK: bgtzalc $2, 1332 # encoding: [0x1c,0x02,0x01,0x4d] blezc $5, 256 # CHECK: blezc $5, 256 # encoding: [0x58,0x05,0x00,0x40] + bltzalc $2, 1332 # CHECK: bltzalc $2, 1332 # encoding: [0x1c,0x42,0x01,0x4d] bgtzc $5, 256 # CHECK: bgtzc $5, 256 # encoding: [0x5c,0x05,0x00,0x40] bitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x7c,0x02,0x20,0x20] + blezalc $2, 1332 # CHECK: blezalc $2, 1332 # encoding: [0x18,0x02,0x01,0x4d] cmp.f.s $f2,$f3,$f4 # CHECK: cmp.f.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x80] cmp.f.d $f2,$f3,$f4 # CHECK: cmp.f.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x80] cmp.un.s $f2,$f3,$f4 # CHECK: cmp.un.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x81] diff --git a/llvm/test/MC/Mips/mips64r6/valid.s b/llvm/test/MC/Mips/mips64r6/valid.s index f341df65427..279dc147a03 100644 --- a/llvm/test/MC/Mips/mips64r6/valid.s +++ b/llvm/test/MC/Mips/mips64r6/valid.s @@ -12,14 +12,20 @@ balc 14572256 # CHECK: balc 14572256 # encoding: [0xe8,0x37,0x96,0xb8] bc 14572256 # CHECK: bc 14572256 # encoding: [0xc8,0x37,0x96,0xb8] beqc $5, $6, 256 # CHECK: beqc $5, $6, 256 # encoding: [0x20,0xa6,0x00,0x40] + beqzalc $2, 1332 # CHECK: beqzalc $2, 1332 # encoding: [0x20,0x02,0x01,0x4d] bnec $5, $6, 256 # CHECK: bnec $5, $6, 256 # encoding: [0x60,0xa6,0x00,0x40] + bnezalc $2, 1332 # CHECK: bnezalc $2, 1332 # encoding: [0x60,0x02,0x01,0x4d] beqzc $5, 72256 # CHECK: beqzc $5, 72256 # encoding: [0xd8,0xa0,0x46,0x90] + bgezalc $2, 1332 # CHECK: bgezalc $2, 1332 # encoding: [0x18,0x42,0x01,0x4d] bnezc $5, 72256 # CHECK: bnezc $5, 72256 # encoding: [0xf8,0xa0,0x46,0x90] bltzc $5, 256 # CHECK: bltzc $5, 256 # encoding: [0x5c,0xa5,0x00,0x40] bgezc $5, 256 # CHECK: bgezc $5, 256 # encoding: [0x58,0xa5,0x00,0x40] + bgtzalc $2, 1332 # CHECK: bgtzalc $2, 1332 # encoding: [0x1c,0x02,0x01,0x4d] blezc $5, 256 # CHECK: blezc $5, 256 # encoding: [0x58,0x05,0x00,0x40] + bltzalc $2, 1332 # CHECK: bltzalc $2, 1332 # encoding: [0x1c,0x42,0x01,0x4d] bgtzc $5, 256 # CHECK: bgtzc $5, 256 # encoding: [0x5c,0x05,0x00,0x40] bitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x7c,0x02,0x20,0x20] + blezalc $2, 1332 # CHECK: blezalc $2, 1332 # encoding: [0x18,0x02,0x01,0x4d] cmp.f.s $f2,$f3,$f4 # CHECK: cmp.f.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x80] cmp.f.d $f2,$f3,$f4 # CHECK: cmp.f.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x80] cmp.un.s $f2,$f3,$f4 # CHECK: cmp.un.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x81] |