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| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-06-27 21:11:40 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-06-27 21:11:40 +0000 |
| commit | 595646f934581ccfdc8eee12a52cc38f69407d86 (patch) | |
| tree | 3d905df56993c548d5a1e975a4a341fa92648790 | |
| parent | 1291a85883f744f6ce64fd4588c8331446dbfed1 (diff) | |
| download | bcm5719-llvm-595646f934581ccfdc8eee12a52cc38f69407d86.tar.gz bcm5719-llvm-595646f934581ccfdc8eee12a52cc38f69407d86.zip | |
get rid of another pseudo op
llvm-svn: 22299
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaISelPattern.cpp | 5 | ||||
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaInstrInfo.td | 2 |
2 files changed, 4 insertions, 3 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp index 6d2cfc63f1c..deb367887d9 100644 --- a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp @@ -1607,8 +1607,9 @@ unsigned AlphaISel::SelectExpr(SDOperand N) { case ISD::GlobalAddress: AlphaLowering.restoreGP(BB); has_sym = true; - BuildMI(BB, Alpha::LOAD_ADDR, 1, Result) - .addGlobalAddress(cast<GlobalAddressSDNode>(N)->getGlobal()); + BuildMI(BB, Alpha::LDQrl, 2, Result) + .addGlobalAddress(cast<GlobalAddressSDNode>(N)->getGlobal()) + .addReg(Alpha::R29); return Result; case ISD::TAILCALL: diff --git a/llvm/lib/Target/Alpha/AlphaInstrInfo.td b/llvm/lib/Target/Alpha/AlphaInstrInfo.td index d660bada06c..cf17feaf64c 100644 --- a/llvm/lib/Target/Alpha/AlphaInstrInfo.td +++ b/llvm/lib/Target/Alpha/AlphaInstrInfo.td @@ -55,7 +55,6 @@ let isCall = 1, //These are evil as they get expanded into multiple instructions to take care of reallocation let Uses = [R29], Defs = [R28] in { - def LOAD_ADDR : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "lda $RA,$DISP">; //Load address def LDQ_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "ldq $RA,$DISP">; //Load quadword def LDS_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "lds $RA,$DISP">; //Load float def LDT_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "ldt $RA,$DISP">; //Load double @@ -363,6 +362,7 @@ def LDLr : MForm<0x28, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldl $RA,$DISP($R def LDQr : MForm<0x29, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldq $RA,$DISP($RB) !gprellow">; //Load quadword def LDBUr : MForm<0x0A, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldbu $RA,$DISP($RB) !gprellow">; //Load zero-extended byte def LDWUr : MForm<0x0C, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldwu $RA,$DISP($RB) !gprellow">; //Load zero-extended word +def LDQrl : MForm<0x29, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldq $RA,$DISP($RB) !literal">; //Load quadword //Loads, float, Rellocated form def LDSr : MForm<0x22, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "lds $RA,$DISP($RB) !gprellow">; //Load S_floating |
