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| author | Kristina Brooks <kristina@nym.hush.com> | 2018-10-02 16:32:32 +0000 |
|---|---|---|
| committer | Kristina Brooks <kristina@nym.hush.com> | 2018-10-02 16:32:32 +0000 |
| commit | 59500f7a0b8a492fec8b571a4a47cf163204247e (patch) | |
| tree | 884057a24d9eff3ad5f8e7819844eb4ea3798db3 | |
| parent | 9cfc8eca70318a38cb073bfd0539c572d3a0ae7b (diff) | |
| download | bcm5719-llvm-59500f7a0b8a492fec8b571a4a47cf163204247e.tar.gz bcm5719-llvm-59500f7a0b8a492fec8b571a4a47cf163204247e.zip | |
[Arm builtins] Remove non-necessary IS check
This patch removes the instruction set check to make the msr APSR_nzcvq,
ip instruction only execute if Thumb2 is used.
The APSR is a subset of the bits of the CPSR
(B.1.3.3 of the Arm v7 A and R ARM [1]) and is only available for A and
R profiles.
However in section B.9.3.11 of the same document we see that:
"In the A and R profiles, APSR_nzcvq is the same as CPSR_f"
"ARM recommends the APSR forms when only the N, Z, C, V, Q, and GE[3:0]
bits are being written."
This patch also make those files assemble for Armv8-M Mainline
architecture profile.
The builtins were cross-compiled for Arm, Aarch64 and Armv6-M, Armv7-M
and Armv7E-M targets.
Cross-compiled tests were executed for Arm target.
[1]: https://developer.arm.com/docs/ddi0406/latest/arm-architecture-reference-manual-armv7-a-and-armv7-r-edition
Patch by hug-dev (Hugues de Valon).
Differential Revision: https://reviews.llvm.org/D51854
llvm-svn: 343601
| -rw-r--r-- | compiler-rt/lib/builtins/arm/aeabi_cdcmp.S | 6 | ||||
| -rw-r--r-- | compiler-rt/lib/builtins/arm/aeabi_cfcmp.S | 6 |
2 files changed, 2 insertions, 10 deletions
diff --git a/compiler-rt/lib/builtins/arm/aeabi_cdcmp.S b/compiler-rt/lib/builtins/arm/aeabi_cdcmp.S index 87dd03dce94..adc2d55d90f 100644 --- a/compiler-rt/lib/builtins/arm/aeabi_cdcmp.S +++ b/compiler-rt/lib/builtins/arm/aeabi_cdcmp.S @@ -55,7 +55,7 @@ DEFINE_COMPILERRT_FUNCTION(__aeabi_cdcmpeq) mov ip, #APSR_C msr APSR_nzcvq, ip #else - msr CPSR_f, #APSR_C + msr APSR_nzcvq, #APSR_C #endif JMP(lr) #endif @@ -115,11 +115,7 @@ DEFINE_COMPILERRT_FUNCTION(__aeabi_cdcmple) movne ip, #(APSR_C) 1: -#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) msr APSR_nzcvq, ip -#else - msr CPSR_f, ip -#endif pop {r0-r3} POP_PC() #endif diff --git a/compiler-rt/lib/builtins/arm/aeabi_cfcmp.S b/compiler-rt/lib/builtins/arm/aeabi_cfcmp.S index c5fee6b6a08..4b1de997687 100644 --- a/compiler-rt/lib/builtins/arm/aeabi_cfcmp.S +++ b/compiler-rt/lib/builtins/arm/aeabi_cfcmp.S @@ -55,7 +55,7 @@ DEFINE_COMPILERRT_FUNCTION(__aeabi_cfcmpeq) mov ip, #APSR_C msr APSR_nzcvq, ip #else - msr CPSR_f, #APSR_C + msr APSR_nzcvq, #APSR_C #endif JMP(lr) #endif @@ -115,11 +115,7 @@ DEFINE_COMPILERRT_FUNCTION(__aeabi_cfcmple) movne ip, #(APSR_C) 1: -#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) msr APSR_nzcvq, ip -#else - msr CPSR_f, ip -#endif pop {r0-r3} POP_PC() #endif |
