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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-01-27 00:53:54 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-01-27 00:53:54 +0000 |
| commit | 590c67507a4fb32c0929c592a30cb2de06b81282 (patch) | |
| tree | 516ad9179ecb7f06f7f5a49f3b90a7d88532d98e | |
| parent | 211e89d4dd386334e3c20814ca99cbe1b9fc12cb (diff) | |
| download | bcm5719-llvm-590c67507a4fb32c0929c592a30cb2de06b81282.tar.gz bcm5719-llvm-590c67507a4fb32c0929c592a30cb2de06b81282.zip | |
GlobalISel: Fix typo in assert messages
llvm-svn: 352301
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp index 99e768e8ed2..77e130f71d4 100644 --- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp +++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp @@ -974,7 +974,7 @@ MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opc, "type mismatch in input list"); assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() == DstOps[0].getLLTTy(*getMRI()).getSizeInBits() && - "input scalars do not exactly cover the outpur vector register"); + "input scalars do not exactly cover the output vector register"); break; } case TargetOpcode::G_BUILD_VECTOR_TRUNC: { @@ -1007,7 +1007,7 @@ MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opc, "type mismatch in input list"); assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() == DstOps[0].getLLTTy(*getMRI()).getSizeInBits() && - "input vectors do not exactly cover the outpur vector register"); + "input vectors do not exactly cover the output vector register"); break; } case TargetOpcode::G_UADDE: { |
