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| author | Hal Finkel <hfinkel@anl.gov> | 2014-11-25 00:30:11 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2014-11-25 00:30:11 +0000 |
| commit | 59016765817633ba125e2c014fd4c6c5de461fa9 (patch) | |
| tree | d57be3581f7f1038b9d988b67d5d74d3e1ca841d | |
| parent | cf82c1e904338791155a160c8ff729f00aa478d9 (diff) | |
| download | bcm5719-llvm-59016765817633ba125e2c014fd4c6c5de461fa9.tar.gz bcm5719-llvm-59016765817633ba125e2c014fd4c6c5de461fa9.zip | |
[PowerPC] Add the 'attn' instruction
The attn instruction is not part of the Power ISA, but is documented in the A2
user manual, and is accepted by the GNU assembler for the A2 and the POWER4+.
Reported as part of PR21650.
llvm-svn: 222712
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrFormats.td | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrInfo.td | 2 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt | 4 | ||||
| -rw-r--r-- | llvm/test/MC/PowerPC/ppc64-encoding-ext.s | 6 |
4 files changed, 18 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFormats.td b/llvm/lib/Target/PowerPC/PPCInstrFormats.td index aa6849744d2..99b266d3365 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrFormats.td +++ b/llvm/lib/Target/PowerPC/PPCInstrFormats.td @@ -385,6 +385,12 @@ class XForm_tlb<bits<10> xo, dag OOL, dag IOL, string asmstr, let RST = 0; } +class XForm_attn<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, + InstrItinClass itin> + : I<opcode, OOL, IOL, asmstr, itin> { + let Inst{21-30} = xo; +} + // This is the same as XForm_base_r3xo, but the first two operands are swapped // when code is emitted. class XForm_base_r3xo_swapped diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td index 8c76c46980d..2ba32a83e66 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -3232,6 +3232,8 @@ def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR), def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR), "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>; +def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>; + //===----------------------------------------------------------------------===// // PowerPC Assembler Instruction Aliases // diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt index 3c2f935714e..24d8fd176f1 100644 --- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt @@ -2274,3 +2274,7 @@ # CHECK: rfid 0x4c 0x00 0x00 0x24 + +# CHECK: attn +0x00 0x00 0x02 0x00 + diff --git a/llvm/test/MC/PowerPC/ppc64-encoding-ext.s b/llvm/test/MC/PowerPC/ppc64-encoding-ext.s index 0ffe0bf6b7c..41711cdc912 100644 --- a/llvm/test/MC/PowerPC/ppc64-encoding-ext.s +++ b/llvm/test/MC/PowerPC/ppc64-encoding-ext.s @@ -3633,3 +3633,9 @@ # CHECK-BE: mtspr 280, 2 # encoding: [0x7c,0x58,0x43,0xa6] # CHECK-LE: mtspr 280, 2 # encoding: [0xa6,0x43,0x58,0x7c] mtasr 2 + +# Processor-Specific Instructions +# CHECK-BE: attn # encoding: [0x00,0x00,0x02,0x00] +# CHECK-LE: attn # encoding: [0x00,0x02,0x00,0x00] + attn + |
