[Docs] fix formatting for bullet list; NFC

llvm-svn: 361341

1 files changed, 11 insertions, 11 deletions

diff --git a/llvm/docs/CodeGenerator.rst b/llvm/docs/CodeGenerator.rst
index 4753acdc6d1..090273524f2 100644
--- a/llvm/docs/CodeGenerator.rst
+++ b/llvm/docs/CodeGenerator.rst
@@ -919,23 +919,23 @@ are created from the shufflevector IR. The shufflevector forms that should be
 handled include:
 
 * Vector select --- Each element of the vector is chosen from either of the
-corresponding elements of the 2 input vectors. This operation may also be
-known as a "blend" or "bitwise select" in target assembly. This type of shuffle
-maps directly to the ``shuffle_vector`` SelectionDAG node.
+  corresponding elements of the 2 input vectors. This operation may also be
+  known as a "blend" or "bitwise select" in target assembly. This type of shuffle
+  maps directly to the ``shuffle_vector`` SelectionDAG node.
 
 * Insert subvector --- A vector is placed into a longer vector type starting
-at index 0. This type of shuffle maps directly to the ``insert_subvector``
-SelectionDAG node with the ``index`` operand set to 0.
+  at index 0. This type of shuffle maps directly to the ``insert_subvector``
+  SelectionDAG node with the ``index`` operand set to 0.
 
 * Extract subvector --- A vector is pulled from a longer vector type starting
-at index 0. This type of shuffle maps directly to the ``extract_subvector``
-SelectionDAG node with the ``index`` operand set to 0.
+  at index 0. This type of shuffle maps directly to the ``extract_subvector``
+  SelectionDAG node with the ``index`` operand set to 0.
 
 * Splat --- All elements of the vector have identical scalar elements. This
-operation may also be known as a "broadcast" or "duplicate" in target assembly.
-The shufflevector IR instruction may change the vector length, so this operation
-may map to multiple SelectionDAG nodes including ``shuffle_vector``,
-``concat_vectors``, ``insert_subvector``, and ``extract_subvector``.
+  operation may also be known as a "broadcast" or "duplicate" in target assembly.
+  The shufflevector IR instruction may change the vector length, so this operation
+  may map to multiple SelectionDAG nodes including ``shuffle_vector``,
+  ``concat_vectors``, ``insert_subvector``, and ``extract_subvector``.
 
 Prior to the existence of the Legalize passes, we required that every target
 `selector`_ supported and handled every operator and type even if they are not