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| author | Matt Beaumont-Gay <matthewbg@google.com> | 2010-12-07 23:26:21 +0000 |
|---|---|---|
| committer | Matt Beaumont-Gay <matthewbg@google.com> | 2010-12-07 23:26:21 +0000 |
| commit | 56de7c2773a72b11f31728208923f89af23cba66 (patch) | |
| tree | 2965158c6fc00a185ebeb9167a510d2deb02b770 | |
| parent | 746660fc7bcd0ba4b2a4663aa00225c7ef3f6f02 (diff) | |
| download | bcm5719-llvm-56de7c2773a72b11f31728208923f89af23cba66.tar.gz bcm5719-llvm-56de7c2773a72b11f31728208923f89af23cba66.zip | |
Fix a warning about a variable which is only used in an assertion.
llvm-svn: 121206
| -rw-r--r-- | llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp index 0376a16e4b0..229e00e65d4 100644 --- a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp +++ b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp @@ -667,9 +667,9 @@ getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const { // [SP, #imm] // {7-0} = imm8 - const MCOperand &MO = MI.getOperand(OpIdx); const MCOperand &MO1 = MI.getOperand(OpIdx + 1); - assert (MO.getReg() == ARM::SP && "Unexpected base register!"); + assert (MI.getOperand(OpIdx).getReg() == ARM::SP && + "Unexpected base register!"); // The immediate is already shifted for the implicit zeroes, so no change // here. return MO1.getImm() & 0xff; |
