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| author | Jonas Paulsson <paulsson@linux.vnet.ibm.com> | 2017-03-31 13:22:59 +0000 |
|---|---|---|
| committer | Jonas Paulsson <paulsson@linux.vnet.ibm.com> | 2017-03-31 13:22:59 +0000 |
| commit | 56bb0857e92c9f578916e83adf692e85f04ee428 (patch) | |
| tree | 72ebcbaa00fed59c4a8755c6c4721672584bac68 | |
| parent | 3add9f9fc75ddf65f5704a1035f5c464d31a1470 (diff) | |
| download | bcm5719-llvm-56bb0857e92c9f578916e83adf692e85f04ee428.tar.gz bcm5719-llvm-56bb0857e92c9f578916e83adf692e85f04ee428.zip | |
[SystemZ] Skip DAGCombining of vector node for older subtargets.
Even on older subtargets that lack vector support, there may be vector values
with just one element in the input program. These are converted during DAG
legalization to scalar values.
The pre-legalize SystemZ DAGCombiner methods should in this circumstance not
touch these nodes. This patch adds a check for this in
SystemZTargetLowering::combineEXTRACT_VECTOR_ELT().
Review: Ulrich Weigand
llvm-svn: 299213
| -rw-r--r-- | llvm/lib/Target/SystemZ/SystemZISelLowering.cpp | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/SystemZ/extract-vector-elt-zEC12.ll | 21 |
2 files changed, 27 insertions, 0 deletions
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp index 6322098e1c3..5078accbaf3 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -4999,6 +4999,12 @@ SDValue SystemZTargetLowering::combineSTORE( SDValue SystemZTargetLowering::combineEXTRACT_VECTOR_ELT( SDNode *N, DAGCombinerInfo &DCI) const { + + // <1 x ..> vectors may be present in the function even without vector + // support, which will be handled during legalization. + if (!Subtarget.hasVector()) + return SDValue(); + // Try to simplify a vector extraction. if (auto *IndexN = dyn_cast<ConstantSDNode>(N->getOperand(1))) { SDValue Op0 = N->getOperand(0); diff --git a/llvm/test/CodeGen/SystemZ/extract-vector-elt-zEC12.ll b/llvm/test/CodeGen/SystemZ/extract-vector-elt-zEC12.ll new file mode 100644 index 00000000000..7bfe5ac8c1a --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/extract-vector-elt-zEC12.ll @@ -0,0 +1,21 @@ +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s +; +; Test that <1 x i8> is legalized properly without vector support. + +define void @autogen_SD18500(i8*) { +; CHECK: .text +BB: + %L5 = load i8, i8* %0 + %I22 = insertelement <1 x i8> undef, i8 %L5, i32 0 + %Cmp53 = icmp ule i1 undef, undef + br label %CF244 + +CF244: ; preds = %CF244, %BB + %Sl119 = select i1 %Cmp53, <1 x i8> %I22, <1 x i8> undef + %Cmp148 = fcmp une float 0x3E03A81780000000, 0x42D92DCD00000000 + br i1 %Cmp148, label %CF244, label %CF241 + +CF241: ; preds = %CF241, %CF244 + %Sl199 = select i1 true, <1 x i8> %Sl119, <1 x i8> zeroinitializer + br label %CF241 +} |
