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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2019-03-22 17:23:55 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2019-03-22 17:23:55 +0000 |
| commit | 564392d752d2b9b2018e401a17145d604c1cb3cc (patch) | |
| tree | 7dcf8800ee852c867e5f859b68868b073dcc6a17 | |
| parent | bfc779e491099213d74c057b5727bde976c7ba02 (diff) | |
| download | bcm5719-llvm-564392d752d2b9b2018e401a17145d604c1cb3cc.tar.gz bcm5719-llvm-564392d752d2b9b2018e401a17145d604c1cb3cc.zip | |
[X86] lowerShuffleAsBitMask - ensure float bit masks are the correct width (PR41203)
llvm-svn: 356784
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 10 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll | 11 |
2 files changed, 16 insertions, 5 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 9f02d2fcca5..5de8ea9c934 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -10385,11 +10385,11 @@ static SDValue lowerShuffleAsBitMask(const SDLoc &DL, MVT VT, SDValue V1, MVT LogicVT = VT; if (EltVT == MVT::f32 || EltVT == MVT::f64) { - Zero = DAG.getConstantFP(0.0, DL, MVT::f64); - AllOnes = DAG.getConstantFP(APInt::getAllOnesValue(64).bitsToDouble(), DL, - EltVT); - LogicVT = MVT::getVectorVT(EltVT == MVT::f64 ? MVT::i64 : MVT::i32, - Mask.size()); + Zero = DAG.getConstantFP(0.0, DL, EltVT); + AllOnes = DAG.getConstantFP( + APFloat::getAllOnesValue(EltVT.getSizeInBits(), true), DL, EltVT); + LogicVT = + MVT::getVectorVT(EltVT == MVT::f64 ? MVT::i64 : MVT::i32, Mask.size()); } else { Zero = DAG.getConstant(0, DL, EltVT); AllOnes = DAG.getAllOnesConstant(DL, EltVT); diff --git a/llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll b/llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll index 18aa9322912..458d670da12 100644 --- a/llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll +++ b/llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll @@ -156,6 +156,17 @@ define <16 x float> @shuffle_v16f32_03_uu_uu_uu_uu_04_uu_uu_uu_uu_11_uu_uu_uu_uu ret <16 x float> %shuffle } +; PR41203 +define <16 x float> @shuffle_v16f32_00_17_02_19_04_21_06_23_08_25_10_27_12_29_14_31(<16 x float> %a) { +; ALL-LABEL: shuffle_v16f32_00_17_02_19_04_21_06_23_08_25_10_27_12_29_14_31: +; ALL: # %bb.0: +; ALL-NEXT: vandps {{.*}}(%rip), %zmm0, %zmm0 +; ALL-NEXT: retq + %tmp1 = shufflevector <16 x float> %a, <16 x float> undef, <16 x i32> <i32 undef, i32 17, i32 undef, i32 19, i32 undef, i32 5, i32 undef, i32 7, i32 undef, i32 9, i32 undef, i32 11, i32 undef, i32 13, i32 undef, i32 15> + %tmp2 = shufflevector <16 x float> %tmp1, <16 x float> <float 0.000000e+00, float undef, float 0.000000e+00, float undef, float 0.000000e+00, float undef, float 0.000000e+00, float undef, float 0.000000e+00, float undef, float 0.000000e+00, float undef, float 0.000000e+00, float undef, float 0.000000e+00, float undef>, <16 x i32> <i32 16, i32 1, i32 18, i32 3, i32 20, i32 5, i32 22, i32 7, i32 24, i32 9, i32 26, i32 11, i32 28, i32 13, i32 30, i32 15> + ret <16 x float> %tmp2 +} + define <16 x i32> @shuffle_v16i32_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00(<16 x i32> %a, <16 x i32> %b) { ; ALL-LABEL: shuffle_v16i32_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00: ; ALL: # %bb.0: |
