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author | Chris Lattner <sabre@nondot.org> | 2008-02-14 18:48:56 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2008-02-14 18:48:56 +0000 |
commit | 558a3ba17f324dbf12f090c58bdccbf859b02354 (patch) | |
tree | 60ec50560ff41c85d65d13bf663f551ca3e90341 | |
parent | 4b3210a3ec210f99c1585500ed40d505f7d1b36c (diff) | |
download | bcm5719-llvm-558a3ba17f324dbf12f090c58bdccbf859b02354.tar.gz bcm5719-llvm-558a3ba17f324dbf12f090c58bdccbf859b02354.zip |
Fix a miscompilation from Dan's recent apintification.
llvm-svn: 47128
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 4 | ||||
-rw-r--r-- | llvm/test/CodeGen/X86/2008-02-14-BitMiscompile.ll | 8 |
2 files changed, 9 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 76cf425499e..f8e1fea679c 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -1437,12 +1437,10 @@ void SelectionDAG::ComputeMaskedBits(SDOperand Op, const APInt &Mask, // We know that the top bits of C-X are clear if X contains less bits // than C (i.e. no wrap-around can happen). For example, 20-X is // positive if we can prove that X is >= 0 and < 16. - - // sign bit clear if (CLHS->getAPIntValue().isNonNegative()) { unsigned NLZ = (CLHS->getAPIntValue()+1).countLeadingZeros(); // NLZ can't be BitWidth with no sign bit - APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ); + APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1); ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero, KnownOne, Depth+1); // If all of the MaskV bits are known to be zero, then we know the output diff --git a/llvm/test/CodeGen/X86/2008-02-14-BitMiscompile.ll b/llvm/test/CodeGen/X86/2008-02-14-BitMiscompile.ll new file mode 100644 index 00000000000..5bf84560a37 --- /dev/null +++ b/llvm/test/CodeGen/X86/2008-02-14-BitMiscompile.ll @@ -0,0 +1,8 @@ +; RUN: llvm-as < %s | llc -march=x86 | grep and +define i32 @test(i1 %A) { + %B = zext i1 %A to i32 ; <i32> [#uses=1] + %C = sub i32 0, %B ; <i32> [#uses=1] + %D = and i32 %C, 255 ; <i32> [#uses=1] + ret i32 %D +} + |