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| author | Hal Finkel <hfinkel@anl.gov> | 2014-03-22 18:24:43 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2014-03-22 18:24:43 +0000 |
| commit | 55805eb562abe19a6bbea29c8f416377cc742963 (patch) | |
| tree | ad3d2ecb763c6b70f29f27fa4c202a1ffe372afb | |
| parent | 68e03bd41f7f862cda7ebefd35d443fee1fd519f (diff) | |
| download | bcm5719-llvm-55805eb562abe19a6bbea29c8f416377cc742963.tar.gz bcm5719-llvm-55805eb562abe19a6bbea29c8f416377cc742963.zip | |
[PowerPC] Fix the VSX v2f64 return register
v2f64 values, like other 128-bit values, are returned under VSX in register
vs34 (Altivec register v2).
llvm-svn: 204543
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCCallingConv.td | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/vsx.ll | 4 |
2 files changed, 5 insertions, 7 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCCallingConv.td b/llvm/lib/Target/PowerPC/PPCCallingConv.td index 7852d895b51..291627a21f2 100644 --- a/llvm/lib/Target/PowerPC/PPCCallingConv.td +++ b/llvm/lib/Target/PowerPC/PPCCallingConv.td @@ -36,7 +36,7 @@ def RetCC_PPC : CallingConv<[ CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4]>>, // Vector types are always returned in V2. - CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToReg<[V2]>> + CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64], CCAssignToReg<[V2]>> ]>; @@ -70,7 +70,7 @@ def RetCC_PPC64_ELF_FIS : CallingConv<[ CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>, CCIfType<[f32], CCAssignToReg<[F1, F2]>>, CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4]>>, - CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToReg<[V2]>> + CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64], CCAssignToReg<[V2]>> ]>; //===----------------------------------------------------------------------===// @@ -104,7 +104,7 @@ def CC_PPC32_SVR4_Common : CallingConv<[ CCIfType<[f32,f64], CCAssignToStack<8, 8>>, // Vectors get 16-byte stack slots that are 16-byte aligned. - CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToStack<16, 16>> + CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64], CCAssignToStack<16, 16>> ]>; // This calling convention puts vector arguments always on the stack. It is used @@ -118,7 +118,7 @@ def CC_PPC32_SVR4_VarArg : CallingConv<[ // put vector arguments in vector registers before putting them on the stack. def CC_PPC32_SVR4 : CallingConv<[ // The first 12 Vector arguments are passed in AltiVec registers. - CCIfType<[v16i8, v8i16, v4i32, v4f32], + CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64], CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13]>>, CCDelegateTo<CC_PPC32_SVR4_Common> diff --git a/llvm/test/CodeGen/PowerPC/vsx.ll b/llvm/test/CodeGen/PowerPC/vsx.ll index ba53b7968c5..6131cd1bb6d 100644 --- a/llvm/test/CodeGen/PowerPC/vsx.ll +++ b/llvm/test/CodeGen/PowerPC/vsx.ll @@ -37,10 +37,8 @@ entry: %v = fadd <2 x double> %a, %b ret <2 x double> %v -; FIXME: Check that the ABI for the return value is correct here! - ; CHECK-LABEL: @test4 -; CHECK: xvadddp {{[0-9]+}}, 34, 35 +; CHECK: xvadddp 34, 34, 35 ; CHECK: blr } |
