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authorTim Northover <tnorthover@apple.com>2016-07-19 19:49:13 +0000
committerTim Northover <tnorthover@apple.com>2016-07-19 19:49:13 +0000
commit554fbd05e89e5326c50d3072037ecc418ed8565a (patch)
tree4b16d5bcca327f2219517369763b8a1f5c347d66
parent5a59b24bdd3b1836884d5792a527b84c6a74b148 (diff)
downloadbcm5719-llvm-554fbd05e89e5326c50d3072037ecc418ed8565a.tar.gz
bcm5719-llvm-554fbd05e89e5326c50d3072037ecc418ed8565a.zip
ARM: move feature for Thumb2 pkhbt/pkhtb onto architectures.
There's not much functional change, but it really is an architectural feature (on v6T2, v7A, v7R and v7EM) rather than something each CPU implements individually. The main functional change is the default behaviour you get when specifying only "-triple". llvm-svn: 276013
Diffstat
-rw-r--r--llvm/lib/Target/ARM/ARM.td46
-rw-r--r--llvm/test/MC/ARM/pkhbt-archs.s17
2 files changed, 31 insertions, 32 deletions
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td
index ef626b66a1e..eb4082d3a18 100644
--- a/llvm/lib/Target/ARM/ARM.td
+++ b/llvm/lib/Target/ARM/ARM.td
@@ -295,7 +295,8 @@ def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
FeatureV7Clrex]>;
def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true",
"Support ARM v8 instructions",
- [HasV7Ops, FeatureAcquireRelease]>;
+ [HasV7Ops, FeatureAcquireRelease,
+ FeatureT2XtPk]>;
def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
"Support ARM v8.1a instructions",
[HasV8Ops]>;
@@ -388,7 +389,8 @@ def ARMv5tej : Architecture<"armv5tej", "ARMv5tej", [HasV5TEOps]>;
def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops]>;
def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops,
- FeatureDSP]>;
+ FeatureDSP,
+ FeatureT2XtPk]>;
def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>;
@@ -409,13 +411,15 @@ def ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops,
FeatureNEON,
FeatureDB,
FeatureDSP,
- FeatureAClass]>;
+ FeatureAClass,
+ FeatureT2XtPk]>;
def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops,
FeatureDB,
FeatureDSP,
FeatureHWDiv,
- FeatureRClass]>;
+ FeatureRClass,
+ FeatureT2XtPk]>;
def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops,
FeatureThumb2,
@@ -570,7 +574,6 @@ def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5,
FeatureSlowFPBrcc,
FeatureHasSlowFPVMLx,
FeatureVMLxForwarding,
- FeatureT2XtPk,
FeatureMP,
FeatureVFP4]>;
@@ -581,7 +584,6 @@ def : ProcessorModel<"cortex-a7", CortexA8Model, [ARMv7a, ProcA7,
FeatureHasVMLxHazards,
FeatureHasSlowFPVMLx,
FeatureVMLxForwarding,
- FeatureT2XtPk,
FeatureMP,
FeatureVFP4,
FeatureHWDiv,
@@ -595,15 +597,13 @@ def : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8,
FeatureSlowFPBrcc,
FeatureHasVMLxHazards,
FeatureHasSlowFPVMLx,
- FeatureVMLxForwarding,
- FeatureT2XtPk]>;
+ FeatureVMLxForwarding]>;
def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9,
FeatureHasRetAddrStack,
FeatureTrustZone,
FeatureHasVMLxHazards,
FeatureVMLxForwarding,
- FeatureT2XtPk,
FeatureFP16,
FeatureAvoidPartialCPSR,
FeatureExpandMLx,
@@ -618,7 +618,6 @@ def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12,
FeatureHasRetAddrStack,
FeatureTrustZone,
FeatureVMLxForwarding,
- FeatureT2XtPk,
FeatureVFP4,
FeatureHWDiv,
FeatureHWDivARM,
@@ -632,7 +631,6 @@ def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15,
FeatureHasRetAddrStack,
FeatureMuxedUnits,
FeatureTrustZone,
- FeatureT2XtPk,
FeatureVFP4,
FeatureMP,
FeatureCheckVLDnAlign,
@@ -647,7 +645,6 @@ def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17,
FeatureTrustZone,
FeatureMP,
FeatureVMLxForwarding,
- FeatureT2XtPk,
FeatureVFP4,
FeatureHWDiv,
FeatureHWDivARM,
@@ -662,7 +659,6 @@ def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait,
FeatureMuxedUnits,
FeatureCheckVLDnAlign,
FeatureVMLxForwarding,
- FeatureT2XtPk,
FeatureFP16,
FeatureAvoidPartialCPSR,
FeatureVFP4,
@@ -672,7 +668,6 @@ def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait,
def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift,
FeatureHasRetAddrStack,
FeatureNEONForFP,
- FeatureT2XtPk,
FeatureVFP4,
FeatureMP,
FeatureHWDiv,
@@ -691,8 +686,7 @@ def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift,
// FIXME: R4 has currently the same ProcessorModel as A8.
def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4,
FeatureHasRetAddrStack,
- FeatureAvoidPartialCPSR,
- FeatureT2XtPk]>;
+ FeatureAvoidPartialCPSR]>;
// FIXME: R4F has currently the same ProcessorModel as A8.
def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4,
@@ -701,8 +695,7 @@ def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4,
FeatureHasSlowFPVMLx,
FeatureVFP3,
FeatureD16,
- FeatureAvoidPartialCPSR,
- FeatureT2XtPk]>;
+ FeatureAvoidPartialCPSR]>;
// FIXME: R5 has currently the same ProcessorModel as A8.
def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5,
@@ -712,8 +705,7 @@ def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5,
FeatureSlowFPBrcc,
FeatureHWDivARM,
FeatureHasSlowFPVMLx,
- FeatureAvoidPartialCPSR,
- FeatureT2XtPk]>;
+ FeatureAvoidPartialCPSR]>;
// FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5.
def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7,
@@ -725,8 +717,7 @@ def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7,
FeatureSlowFPBrcc,
FeatureHWDivARM,
FeatureHasSlowFPVMLx,
- FeatureAvoidPartialCPSR,
- FeatureT2XtPk]>;
+ FeatureAvoidPartialCPSR]>;
def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r,
FeatureHasRetAddrStack,
@@ -737,8 +728,7 @@ def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r,
FeatureSlowFPBrcc,
FeatureHWDivARM,
FeatureHasSlowFPVMLx,
- FeatureAvoidPartialCPSR,
- FeatureT2XtPk]>;
+ FeatureAvoidPartialCPSR]>;
def : ProcNoItin<"cortex-m3", [ARMv7m, ProcM3]>;
def : ProcNoItin<"sc300", [ARMv7m, ProcM3]>;
@@ -755,42 +745,36 @@ def : ProcNoItin<"cortex-m7", [ARMv7em,
def : ProcNoItin<"cortex-a32", [ARMv8a,
FeatureHWDiv,
FeatureHWDivARM,
- FeatureT2XtPk,
FeatureCrypto,
FeatureCRC]>;
def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35,
FeatureHWDiv,
FeatureHWDivARM,
- FeatureT2XtPk,
FeatureCrypto,
FeatureCRC]>;
def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53,
FeatureHWDiv,
FeatureHWDivARM,
- FeatureT2XtPk,
FeatureCrypto,
FeatureCRC]>;
def : ProcNoItin<"cortex-a57", [ARMv8a, ProcA57,
FeatureHWDiv,
FeatureHWDivARM,
- FeatureT2XtPk,
FeatureCrypto,
FeatureCRC]>;
def : ProcNoItin<"cortex-a72", [ARMv8a, ProcA72,
FeatureHWDiv,
FeatureHWDivARM,
- FeatureT2XtPk,
FeatureCrypto,
FeatureCRC]>;
def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73,
FeatureHWDiv,
FeatureHWDivARM,
- FeatureT2XtPk,
FeatureCrypto,
FeatureCRC]>;
@@ -798,7 +782,6 @@ def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73,
def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift,
FeatureHasRetAddrStack,
FeatureNEONForFP,
- FeatureT2XtPk,
FeatureVFP4,
FeatureMP,
FeatureHWDiv,
@@ -812,7 +795,6 @@ def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift,
def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynosM1,
FeatureHWDiv,
FeatureHWDivARM,
- FeatureT2XtPk,
FeatureCrypto,
FeatureCRC]>;
diff --git a/llvm/test/MC/ARM/pkhbt-archs.s b/llvm/test/MC/ARM/pkhbt-archs.s
new file mode 100644
index 00000000000..a54a724db46
--- /dev/null
+++ b/llvm/test/MC/ARM/pkhbt-archs.s
@@ -0,0 +1,17 @@
+@ RUN: llvm-mc -triple thumbv7 %s -o - -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK-VALID
+@ RUN: llvm-mc -triple thumbv8 %s -o - -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK-VALID
+@ RUN: llvm-mc -triple thumbv7em %s -o - -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK-VALID
+@ RUN: llvm-mc -triple thumbv6t2 %s -o - -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK-VALID
+
+@ RUN: not llvm-mc -triple thumbv6 %s -o - -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK-INVALID
+@ RUN: not llvm-mc -triple thumbv7m %s -o - -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK-INVALID
+@ RUN: not llvm-mc -triple thumbv8m.main %s -o - -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK-INVALID
+@ RUN: not llvm-mc -triple thumbv8m.base %s -o - -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK-INVALID
+
+ @ Instruction is "v6T2, v7" in ARMARM-AR, "v7em" in ARMARM-M. So it's
+ @ valid on everything v6t2 upwards, except v7m. Also apparently not on
+ @ v8m (going by present behaviour).
+ pkhbt r1, r2, r3, lsl #24
+
+@ CHECK-VALID: pkhbt r1, r2, r3, lsl #24 @ encoding: [0xc2,0xea,0x03,0x61]
+@ CHECK-INVALID: error:
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