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| author | Venkatraman Govindaraju <venkatra@cs.wisc.edu> | 2013-05-16 23:53:29 +0000 |
|---|---|---|
| committer | Venkatraman Govindaraju <venkatra@cs.wisc.edu> | 2013-05-16 23:53:29 +0000 |
| commit | 54bf611c795a89ac43c36dec5ecb604d5c5364b6 (patch) | |
| tree | 1793f50bac088ba082f80f063d9b091f8751c812 | |
| parent | 9c93059aa403ebc9e6c1a9e111b5eb38ee89d5fc (diff) | |
| download | bcm5719-llvm-54bf611c795a89ac43c36dec5ecb604d5c5364b6.tar.gz bcm5719-llvm-54bf611c795a89ac43c36dec5ecb604d5c5364b6.zip | |
[Sparc] Prevent instructions that defines or uses %o7 to be in call's delay slot.
llvm-svn: 182063
| -rw-r--r-- | llvm/lib/Target/Sparc/DelaySlotFiller.cpp | 14 | ||||
| -rw-r--r-- | llvm/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll | 17 |
2 files changed, 26 insertions, 5 deletions
diff --git a/llvm/lib/Target/Sparc/DelaySlotFiller.cpp b/llvm/lib/Target/Sparc/DelaySlotFiller.cpp index 6123773d5f4..db3f15900bb 100644 --- a/llvm/lib/Target/Sparc/DelaySlotFiller.cpp +++ b/llvm/lib/Target/Sparc/DelaySlotFiller.cpp @@ -61,8 +61,9 @@ namespace { bool isDelayFiller(MachineBasicBlock &MBB, MachineBasicBlock::iterator candidate); - void insertCallUses(MachineBasicBlock::iterator MI, - SmallSet<unsigned, 32>& RegUses); + void insertCallDefsUses(MachineBasicBlock::iterator MI, + SmallSet<unsigned, 32>& RegDefs, + SmallSet<unsigned, 32>& RegUses); void insertDefsUses(MachineBasicBlock::iterator MI, SmallSet<unsigned, 32>& RegDefs, @@ -150,7 +151,7 @@ Filler::findDelayInstr(MachineBasicBlock &MBB, //Call's delay filler can def some of call's uses. if (slot->isCall()) - insertCallUses(slot, RegUses); + insertCallDefsUses(slot, RegDefs, RegUses); else insertDefsUses(slot, RegDefs, RegUses); @@ -230,9 +231,12 @@ bool Filler::delayHasHazard(MachineBasicBlock::iterator candidate, } -void Filler::insertCallUses(MachineBasicBlock::iterator MI, - SmallSet<unsigned, 32>& RegUses) +void Filler::insertCallDefsUses(MachineBasicBlock::iterator MI, + SmallSet<unsigned, 32>& RegDefs, + SmallSet<unsigned, 32>& RegUses) { + //Call defines o7, which is visible to the instruction in delay slot. + RegDefs.insert(SP::O7); switch(MI->getOpcode()) { default: llvm_unreachable("Unknown opcode."); diff --git a/llvm/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll b/llvm/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll index 71fdb4e0d60..a0878d34828 100644 --- a/llvm/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll +++ b/llvm/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll @@ -87,4 +87,21 @@ entry: ret i32 0 } +define i32 @prevent_o7_in_call_delay_slot(i32 %i0) { +entry: +;CHECK: prevent_o7_in_call_delay_slot +;CHECK: add %i0, 2, %o5 +;CHECK: add %i0, 3, %o7 +;CHECK: add %o5, %o7, %o0 +;CHECK: call bar +;CHECK-NEXT: nop + %0 = add nsw i32 %i0, 2 + %1 = add nsw i32 %i0, 3 + tail call void asm sideeffect "", "r,r,~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{o0},~{o1},~{o2},~{o3},~{o4}"(i32 %0, i32 %1) + %2 = add nsw i32 %0, %1 + %3 = tail call i32 @bar(i32 %2) + ret i32 %3 +} + + declare i32 @func(i32*) |
