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| author | Craig Topper <craig.topper@intel.com> | 2017-12-20 00:46:09 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-12-20 00:46:09 +0000 |
| commit | 54b3f718e4deb58c9a63d5e7280f4df688d32ffd (patch) | |
| tree | 562c5b9b934a82a9802ca6a6b2f29bb9cadb97bd | |
| parent | e8ba3ec4537eecd7d2947e89a35338f884bba96c (diff) | |
| download | bcm5719-llvm-54b3f718e4deb58c9a63d5e7280f4df688d32ffd.tar.gz bcm5719-llvm-54b3f718e4deb58c9a63d5e7280f4df688d32ffd.zip | |
[X86] Add more CPUID bits to cpuid.h to match gcc and support icelake features.
llvm-svn: 321129
| -rw-r--r-- | clang/lib/Headers/cpuid.h | 19 |
1 files changed, 14 insertions, 5 deletions
diff --git a/clang/lib/Headers/cpuid.h b/clang/lib/Headers/cpuid.h index 2dd0add236b..3ae90de0b91 100644 --- a/clang/lib/Headers/cpuid.h +++ b/clang/lib/Headers/cpuid.h @@ -173,16 +173,24 @@ #define bit_AVX512VL 0x80000000 /* Features in %ecx for leaf 7 sub-leaf 0 */ -#define bit_PREFTCHWT1 0x00000001 -#define bit_AVX512VBMI 0x00000002 -#define bit_PKU 0x00000004 -#define bit_OSPKE 0x00000010 +#define bit_PREFTCHWT1 0x00000001 +#define bit_AVX512VBMI 0x00000002 +#define bit_PKU 0x00000004 +#define bit_OSPKE 0x00000010 +#define bit_AVX512VBMI2 0x00000040 +#define bit_SHSTK 0x00000080 +#define bit_GFNI 0x00000100 +#define bit_VAES 0x00000200 +#define bit_VPCLMULQDQ 0x00000400 +#define bit_AVX512VNNI 0x00000800 +#define bit_AVX512BITALG 0x00001000 #define bit_AVX512VPOPCNTDQ 0x00004000 -#define bit_RDPID 0x00400000 +#define bit_RDPID 0x00400000 /* Features in %edx for leaf 7 sub-leaf 0 */ #define bit_AVX5124VNNIW 0x00000004 #define bit_AVX5124FMAPS 0x00000008 +#define bit_IBT 0x00100000 /* Features in %eax for leaf 13 sub-leaf 1 */ #define bit_XSAVEOPT 0x00000001 @@ -192,6 +200,7 @@ /* Features in %ecx for leaf 0x80000001 */ #define bit_LAHF_LM 0x00000001 #define bit_ABM 0x00000020 +#define bit_LZCNT bit_ABM /* for gcc compat */ #define bit_SSE4a 0x00000040 #define bit_PRFCHW 0x00000100 #define bit_XOP 0x00000800 |
