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| author | Richard Osborne <richard@xmos.com> | 2011-05-31 14:47:36 +0000 |
|---|---|---|
| committer | Richard Osborne <richard@xmos.com> | 2011-05-31 14:47:36 +0000 |
| commit | 542f9a2bcf5d7a1512e1e45568a89f53b40d18ce (patch) | |
| tree | 5f8731750ea4f64503746f4c0832655ed7593b6e | |
| parent | 36d027f7f612b2cc3050997f3a6b9a02329d4a4f (diff) | |
| download | bcm5719-llvm-542f9a2bcf5d7a1512e1e45568a89f53b40d18ce.tar.gz bcm5719-llvm-542f9a2bcf5d7a1512e1e45568a89f53b40d18ce.zip | |
Add XCore intrinsic for crc32.
llvm-svn: 132336
| -rw-r--r-- | llvm/include/llvm/IntrinsicsXCore.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/XCore/XCoreInstrInfo.td | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/XCore/bitrev.ll | 9 | ||||
| -rw-r--r-- | llvm/test/CodeGen/XCore/misc-intrinsics.ll | 17 |
4 files changed, 25 insertions, 10 deletions
diff --git a/llvm/include/llvm/IntrinsicsXCore.td b/llvm/include/llvm/IntrinsicsXCore.td index e633af045c3..951f7dd700c 100644 --- a/llvm/include/llvm/IntrinsicsXCore.td +++ b/llvm/include/llvm/IntrinsicsXCore.td @@ -11,6 +11,7 @@ let TargetPrefix = "xcore" in { // All intrinsics start with "llvm.xcore.". // Miscellaneous instructions. def int_xcore_bitrev : Intrinsic<[llvm_i32_ty],[llvm_i32_ty],[IntrNoMem]>; + def int_xcore_crc32 : Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],[IntrNoMem]>; def int_xcore_getid : Intrinsic<[llvm_i32_ty],[],[IntrNoMem]>; def int_xcore_getps : Intrinsic<[llvm_i32_ty],[llvm_i32_ty]>; def int_xcore_setps : Intrinsic<[],[llvm_i32_ty, llvm_i32_ty]>; diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.td b/llvm/lib/Target/XCore/XCoreInstrInfo.td index 789546ed304..1647db5d787 100644 --- a/llvm/lib/Target/XCore/XCoreInstrInfo.td +++ b/llvm/lib/Target/XCore/XCoreInstrInfo.td @@ -472,7 +472,13 @@ def REMU_l3r : FL3R<"remu", urem>; } def XOR_l3r : FL3R<"xor", xor>; defm ASHR : FL3R_L2RBITP<"ashr", sra>; -// TODO crc32, crc8, inpw, outpw + +let Constraints = "$src1 = $dst" in +def CRC_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), + "crc32 $dst, $src2, $src3", + [(set GRRegs:$dst, (int_xcore_crc32 GRRegs:$src1, GRRegs:$src2, GRRegs:$src3))]>; + +// TODO inpw, outpw let mayStore=1 in { def ST16_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), "st16 $val, $addr[$offset]", diff --git a/llvm/test/CodeGen/XCore/bitrev.ll b/llvm/test/CodeGen/XCore/bitrev.ll deleted file mode 100644 index 9f0dc3923b7..00000000000 --- a/llvm/test/CodeGen/XCore/bitrev.ll +++ /dev/null @@ -1,9 +0,0 @@ -; RUN: llc < %s -march=xcore | FileCheck %s -declare i32 @llvm.xcore.bitrev(i32) - -define i32 @bitrev(i32 %val) { -; CHECK: bitrev: -; CHECK: bitrev r0, r0 - %result = call i32 @llvm.xcore.bitrev(i32 %val) - ret i32 %result -} diff --git a/llvm/test/CodeGen/XCore/misc-intrinsics.ll b/llvm/test/CodeGen/XCore/misc-intrinsics.ll new file mode 100644 index 00000000000..0c684886eed --- /dev/null +++ b/llvm/test/CodeGen/XCore/misc-intrinsics.ll @@ -0,0 +1,17 @@ +; RUN: llc < %s -march=xcore | FileCheck %s +declare i32 @llvm.xcore.bitrev(i32) +declare i32 @llvm.xcore.crc32(i32, i32, i32) + +define i32 @bitrev(i32 %val) { +; CHECK: bitrev: +; CHECK: bitrev r0, r0 + %result = call i32 @llvm.xcore.bitrev(i32 %val) + ret i32 %result +} + +define i32 @crc32(i32 %crc, i32 %data, i32 %poly) { +; CHECK: crc32: +; CHECK: crc32 r0, r1, r2 + %result = call i32 @llvm.xcore.crc32(i32 %crc, i32 %data, i32 %poly) + ret i32 %result +} |
