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author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-03-18 13:16:11 +0000 |
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committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-03-18 13:16:11 +0000 |
commit | 541992203dfc2f2e62309dfc0860677b685a80de (patch) | |
tree | bcf92395616408f1910c2f2ba90888376b828d27 | |
parent | 40f6d6ad0bee6d2c610d24fdbe8bd9076ea033f9 (diff) | |
download | bcm5719-llvm-541992203dfc2f2e62309dfc0860677b685a80de.tar.gz bcm5719-llvm-541992203dfc2f2e62309dfc0860677b685a80de.zip |
[X86][Btver2] Strip default latency/resource values. NFCI.
llvm-svn: 327795
-rw-r--r-- | llvm/lib/Target/X86/X86ScheduleBtVer2.td | 17 |
1 files changed, 7 insertions, 10 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleBtVer2.td b/llvm/lib/Target/X86/X86ScheduleBtVer2.td index 302dc120360..b5310cdf683 100644 --- a/llvm/lib/Target/X86/X86ScheduleBtVer2.td +++ b/llvm/lib/Target/X86/X86ScheduleBtVer2.td @@ -136,7 +136,6 @@ def : WriteRes<WriteLEA, [JALU01]>; // FIXME: Why do bitcounts use WriteIMul? def JWriteLZCNT : SchedWriteRes<[JALU01]> { - let Latency = 1; } def JWriteLZCNTLd : SchedWriteRes<[JLAGU, JALU01]> { let Latency = 4; @@ -373,28 +372,28 @@ defm : JWriteResFpuPair<WriteCLMul, [JFPU0, JVIMUL], 2>; def JWriteDPPS: SchedWriteRes<[JFPU0, JFPU1]> { let Latency = 11; - let ResourceCycles = [3,3]; + let ResourceCycles = [3, 3]; let NumMicroOps = 5; } def : InstRW<[JWriteDPPS], (instrs DPPSrri, VDPPSrri)>; def JWriteDPPSLd: SchedWriteRes<[JLAGU, JFPU0, JFPU1]> { let Latency = 16; - let ResourceCycles = [1,3,3]; + let ResourceCycles = [1, 3, 3]; let NumMicroOps = 6; } def : InstRW<[JWriteDPPSLd], (instrs DPPSrmi, VDPPSrmi)>; def JWriteDPPD: SchedWriteRes<[JFPU0, JFPU1]> { let Latency = 9; - let ResourceCycles = [3,3]; + let ResourceCycles = [3, 3]; let NumMicroOps = 3; } def : InstRW<[JWriteDPPD], (instrs DPPDrri, VDPPDrri)>; def JWriteDPPDLd: SchedWriteRes<[JLAGU, JFPU0, JFPU1]> { let Latency = 14; - let ResourceCycles = [1,3,3]; + let ResourceCycles = [1, 3, 3]; let NumMicroOps = 3; } def : InstRW<[JWriteDPPDLd], (instrs DPPDrmi, VDPPDrmi)>; @@ -424,26 +423,24 @@ def : InstRW<[JWriteCVT3], (instrs VCVTPS2PHrr, VCVTPH2PSrr)>; def JWriteCVT3St: SchedWriteRes<[JFPU1, JSAGU]> { let Latency = 3; - let ResourceCycles = [1, 1]; } def : InstRW<[JWriteCVT3St], (instrs VCVTPS2PHmr)>; def JWriteCVT3Ld: SchedWriteRes<[JLAGU, JFPU1]> { let Latency = 8; - let ResourceCycles = [1, 1]; } def : InstRW<[JWriteCVT3Ld], (instrs VCVTPH2PSrm)>; def JWriteCVTPS2PHY: SchedWriteRes<[JFPU1, JFPU01]> { let Latency = 6; - let ResourceCycles = [2,2]; + let ResourceCycles = [2, 2]; let NumMicroOps = 3; } def : InstRW<[JWriteCVTPS2PHY], (instrs VCVTPS2PHYrr)>; def JWriteCVTPS2PHYSt: SchedWriteRes<[JFPU1, JFPU01, JSAGU]> { let Latency = 11; - let ResourceCycles = [2,2,1]; + let ResourceCycles = [2, 2, 1]; let NumMicroOps = 3; } def : InstRW<[JWriteCVTPS2PHYSt], (instrs VCVTPS2PHYmr)>; @@ -457,7 +454,7 @@ def : InstRW<[JWriteCVTPH2PSY], (instrs VCVTPH2PSYrr)>; def JWriteCVTPH2PSYLd: SchedWriteRes<[JLAGU, JFPU1]> { let Latency = 8; - let ResourceCycles = [1,2]; + let ResourceCycles = [1, 2]; let NumMicroOps = 2; } def : InstRW<[JWriteCVTPH2PSYLd], (instrs VCVTPH2PSYrm)>; |