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| author | Bernard Ogden <bogden@arm.com> | 2013-10-14 13:17:07 +0000 |
|---|---|---|
| committer | Bernard Ogden <bogden@arm.com> | 2013-10-14 13:17:07 +0000 |
| commit | 53169762d0bd7bc50582659f14f3e9a9e4999a0d (patch) | |
| tree | 864e63a9a8ae5c71ca6fbf97760b41821791afaf | |
| parent | 4400cde89ad469d79e80d39c626c9644eb83d912 (diff) | |
| download | bcm5719-llvm-53169762d0bd7bc50582659f14f3e9a9e4999a0d.tar.gz bcm5719-llvm-53169762d0bd7bc50582659f14f3e9a9e4999a0d.zip | |
Add Cortex-A57 support
llvm-svn: 192591
| -rw-r--r-- | llvm/lib/Target/ARM/ARM.td | 9 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMSubtarget.h | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/2010-09-29-mc-asm-header-test.ll | 13 |
3 files changed, 23 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td index 9de29c1cb1f..5fab93040cf 100644 --- a/llvm/lib/Target/ARM/ARM.td +++ b/llvm/lib/Target/ARM/ARM.td @@ -203,6 +203,12 @@ def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", FeatureTrustZone, FeatureT2XtPk, FeatureCrypto]>; +def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", + "Cortex-A57 ARM processors", + [FeatureMP, FeatureHWDiv, FeatureHWDivARM, + FeatureTrustZone, FeatureT2XtPk, + FeatureCrypto]>; + def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5", "Cortex-R5 ARM processors", [FeatureSlowFPBrcc, @@ -326,6 +332,9 @@ def : ProcessorModel<"swift", SwiftModel, def : ProcNoItin<"cortex-a53", [ProcA53, HasV8Ops, FeatureAClass, FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2]>; +def : ProcNoItin<"cortex-a57", [ProcA57, HasV8Ops, FeatureAClass, + FeatureDB, FeatureFPARMv8, + FeatureNEON, FeatureDSPThumb2]>; //===----------------------------------------------------------------------===// // Register File Description diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h index 5dc5975eb86..9cc3a71f891 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.h +++ b/llvm/lib/Target/ARM/ARMSubtarget.h @@ -31,7 +31,7 @@ class TargetOptions; class ARMSubtarget : public ARMGenSubtargetInfo { protected: enum ARMProcFamilyEnum { - Others, CortexA5, CortexA8, CortexA9, CortexA15, CortexR5, Swift, CortexA53 + Others, CortexA5, CortexA8, CortexA9, CortexA15, CortexR5, Swift, CortexA53, CortexA57 }; enum ARMProcClassEnum { None, AClass, RClass, MClass diff --git a/llvm/test/CodeGen/ARM/2010-09-29-mc-asm-header-test.ll b/llvm/test/CodeGen/ARM/2010-09-29-mc-asm-header-test.ll index 3501fb7ec7c..e9e9def8d3b 100644 --- a/llvm/test/CodeGen/ARM/2010-09-29-mc-asm-header-test.ll +++ b/llvm/test/CodeGen/ARM/2010-09-29-mc-asm-header-test.ll @@ -14,6 +14,7 @@ ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 | FileCheck %s --check-prefix=CORTEX-M4 ; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5 | FileCheck %s --check-prefix=CORTEX-R5 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a53 | FileCheck %s --check-prefix=CORTEX-A53 +; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a57 | FileCheck %s --check-prefix=CORTEX-A57 ; This tests that MC/asm header conversion is smooth and that build attributes are correct ; @@ -147,6 +148,18 @@ ; CORTEX-A53: .eabi_attribute 25, 1 ; CORTEX-A53: .eabi_attribute 44, 2 +; CORTEX-A57: .cpu cortex-a57 +; CORTEX-A57: .eabi_attribute 6, 14 +; CORTEX-A57: .eabi_attribute 7, 65 +; CORTEX-A57: .eabi_attribute 8, 1 +; CORTEX-A57: .eabi_attribute 9, 2 +; CORTEX-A57: .fpu crypto-neon-fp-armv8 +; CORTEX-A57: .eabi_attribute 10, 7 +; CORTEX-A57: .eabi_attribute 12, 3 +; CORTEX-A57: .eabi_attribute 24, 1 +; CORTEX-A57: .eabi_attribute 25, 1 +; CORTEX-A57: .eabi_attribute 44, 2 + define i32 @f(i64 %z) { ret i32 0 } |
