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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-06-23 01:26:16 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-06-23 01:26:16 +0000 |
| commit | 529cf25e607b8500fae5295544bfd43fe2d13ebe (patch) | |
| tree | 8de72afca42d4c63536aaae738d1f864ad0b02ba | |
| parent | cb6dae22e2984558f983b7a64c70c2b7b08793aa (diff) | |
| download | bcm5719-llvm-529cf25e607b8500fae5295544bfd43fe2d13ebe.tar.gz bcm5719-llvm-529cf25e607b8500fae5295544bfd43fe2d13ebe.zip | |
AMDGPU: readlane/writelane do not read exec
llvm-svn: 273525
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 25 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstructions.td | 3 |
2 files changed, 26 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 05c73f901ec..d23b14c8d6c 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -1631,6 +1631,29 @@ static unsigned findImplicitSGPRRead(const MachineInstr &MI) { return AMDGPU::NoRegister; } +static bool shouldReadExec(const MachineInstr &MI) { + if (SIInstrInfo::isVALU(MI)) { + switch (MI.getOpcode()) { + case AMDGPU::V_READLANE_B32: + case AMDGPU::V_READLANE_B32_si: + case AMDGPU::V_READLANE_B32_vi: + case AMDGPU::V_WRITELANE_B32: + case AMDGPU::V_WRITELANE_B32_si: + case AMDGPU::V_WRITELANE_B32_vi: + return false; + } + + return true; + } + + if (SIInstrInfo::isGenericOpcode(MI.getOpcode()) || + SIInstrInfo::isSALU(MI) || + SIInstrInfo::isSMRD(MI)) + return false; + + return true; +} + bool SIInstrInfo::verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const { uint16_t Opcode = MI->getOpcode(); @@ -1751,7 +1774,7 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr *MI, // Make sure we aren't losing exec uses in the td files. This mostly requires // being careful when using let Uses to try to add other use registers. - if (!isGenericOpcode(Opcode) && !isSALU(Opcode) && !isSMRD(Opcode)) { + if (shouldReadExec(*MI)) { if (!MI->hasRegisterImplicitUseOperand(AMDGPU::EXEC)) { ErrInfo = "VALU instruction does not implicitly read exec mask"; return false; diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index 23717daaa16..db1038d9fdf 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -1586,7 +1586,8 @@ defm V_SUBBREV_U32 : VOP2bInst <vop2<0x2a, 0x1e>, "v_subbrev_u32", } // End isCommutable = 1 -let isConvergent = 1 in { +// These are special and do not read the exec mask. +let isConvergent = 1, Uses = []<Register> in { defm V_READLANE_B32 : VOP2SI_3VI_m < vop3 <0x001, 0x289>, |
