summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorJim Grosbach <grosbach@apple.com>2009-09-28 22:08:06 +0000
committerJim Grosbach <grosbach@apple.com>2009-09-28 22:08:06 +0000
commit5264202a383162edb660bf333dd496b255fd9e6c (patch)
treec6d02cf3a0cbcad13def1d55e4ccc9c3e98c3138
parent9021fc7026be8b3f59e2c9263a2e80365d96543d (diff)
downloadbcm5719-llvm-5264202a383162edb660bf333dd496b255fd9e6c.tar.gz
bcm5719-llvm-5264202a383162edb660bf333dd496b255fd9e6c.zip
Adjust processFunctionBeforeCalleeSavedScan() to correctly reserve a stack
slot for the register scavenger when compiling Thumb1 functions. llvm-svn: 83023
-rw-r--r--llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp6
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
index ab3dcd6992c..9b923093923 100644
--- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
@@ -536,7 +536,8 @@ ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
}
}
- if (CSRegClasses[i] == ARM::GPRRegisterClass) {
+ if (CSRegClasses[i] == ARM::GPRRegisterClass ||
+ CSRegClasses[i] == ARM::tGPRRegisterClass) {
if (Spilled) {
NumGPRSpills++;
@@ -667,7 +668,8 @@ ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
NumExtras--;
}
}
- while (NumExtras && !UnspilledCS2GPRs.empty()) {
+ while (NumExtras && !UnspilledCS2GPRs.empty() &&
+ !AFI->isThumb1OnlyFunction()) {
unsigned Reg = UnspilledCS2GPRs.back();
UnspilledCS2GPRs.pop_back();
if (!isReservedReg(MF, Reg)) {
OpenPOWER on IntegriCloud