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| author | Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> | 2019-11-20 15:09:08 +0300 |
|---|---|---|
| committer | Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> | 2019-11-20 15:56:45 +0300 |
| commit | 525f9c0be538ba93e01b3a783d62b9f562e5a6b4 (patch) | |
| tree | 1485361b4f15fee072bd2a217b397fba7424513c | |
| parent | 5e0b7df4db237b53d50799e8cbc5ce7d3872c9dd (diff) | |
| download | bcm5719-llvm-525f9c0be538ba93e01b3a783d62b9f562e5a6b4.tar.gz bcm5719-llvm-525f9c0be538ba93e01b3a783d62b9f562e5a6b4.zip | |
[AMDGPU][DPP] Corrected DPP combiner
Added a check to make sure that the selected dpp opcode is supported by target.
Reviewers: vpykhtin, arsenm, rampitec
Differential Revision: https://reviews.llvm.org/D70402
| -rw-r--r-- | llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp b/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp index edf2b5f62b9..10e2c3a263f 100644 --- a/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp +++ b/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp @@ -104,6 +104,9 @@ public: AU.setPreservesCFG(); MachineFunctionPass::getAnalysisUsage(AU); } + +private: + int getDPPOp(unsigned Op) const; }; } // end anonymous namespace @@ -118,13 +121,13 @@ FunctionPass *llvm::createGCNDPPCombinePass() { return new GCNDPPCombine(); } -static int getDPPOp(unsigned Op) { +int GCNDPPCombine::getDPPOp(unsigned Op) const { auto DPP32 = AMDGPU::getDPPOp32(Op); - if (DPP32 != -1) - return DPP32; - - auto E32 = AMDGPU::getVOPe32(Op); - return E32 != -1 ? AMDGPU::getDPPOp32(E32) : -1; + if (DPP32 == -1) { + auto E32 = AMDGPU::getVOPe32(Op); + DPP32 = (E32 == -1)? -1 : AMDGPU::getDPPOp32(E32); + } + return (DPP32 == -1 || TII->pseudoToMCOpcode(DPP32) == -1) ? -1 : DPP32; } // tracks the register operand definition and returns: |
