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| author | Sanjay Patel <spatel@rotateright.com> | 2016-10-17 20:41:39 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2016-10-17 20:41:39 +0000 |
| commit | 523cd8290a68821124de2fe52240c1c1f1439895 (patch) | |
| tree | b0c4226488789f52f4799fca7ebfcd91215112d5 | |
| parent | fac32f3f6a61f6abfa3794c2693bcd66c962eba2 (diff) | |
| download | bcm5719-llvm-523cd8290a68821124de2fe52240c1c1f1439895.tar.gz bcm5719-llvm-523cd8290a68821124de2fe52240c1c1f1439895.zip | |
[DAG] use isConstOrConstSplat in ComputeNumSignBits to optimize SRA
The scalar version of this pattern was noted in:
https://reviews.llvm.org/D25485
and fixed with:
https://reviews.llvm.org/rL284395
More refactoring of the constant/splat helpers is needed and will happen in follow-up patches.
Differential Revision: https://reviews.llvm.org/D25685
llvm-svn: 284424
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/sar_fold64.ll | 10 |
2 files changed, 1 insertions, 11 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 776b0eae0d1..56945b4bf98 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -2697,7 +2697,7 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const { if (Tmp2 == 1) return 1; // Handle NEG. - if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) + if (ConstantSDNode *CLHS = isConstOrConstSplat(Op.getOperand(0))) if (CLHS->isNullValue()) { APInt KnownZero, KnownOne; computeKnownBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1); diff --git a/llvm/test/CodeGen/X86/sar_fold64.ll b/llvm/test/CodeGen/X86/sar_fold64.ll index 80c632b1f6a..817a2dbe671 100644 --- a/llvm/test/CodeGen/X86/sar_fold64.ll +++ b/llvm/test/CodeGen/X86/sar_fold64.ll @@ -80,16 +80,6 @@ define <4 x i32> @all_sign_bit_ashr_vec(<4 x i32> %x) { ; CHECK-NEXT: pxor %xmm1, %xmm1 ; CHECK-NEXT: psubd %xmm0, %xmm1 ; CHECK-NEXT: movdqa %xmm1, %xmm0 -; CHECK-NEXT: psrad $31, %xmm0 -; CHECK-NEXT: movdqa %xmm1, %xmm2 -; CHECK-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1] -; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3] -; CHECK-NEXT: movdqa %xmm1, %xmm0 -; CHECK-NEXT: psrad $5, %xmm0 -; CHECK-NEXT: psrad $1, %xmm1 -; CHECK-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] -; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] -; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] ; CHECK-NEXT: retq ; %and = and <4 x i32> %x, <i32 1, i32 1, i32 1 , i32 1> |
