diff options
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-04-17 02:03:08 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-04-17 02:03:08 +0000 |
| commit | 51df0c196587c9e2e341d657e86abd5d70da177a (patch) | |
| tree | 1931246d915d7dc590ea2968aeec459628d74260 | |
| parent | 100b24abc5a08552e0d94371561785d688249438 (diff) | |
| download | bcm5719-llvm-51df0c196587c9e2e341d657e86abd5d70da177a.tar.gz bcm5719-llvm-51df0c196587c9e2e341d657e86abd5d70da177a.zip | |
R600/SI: Fix zext from i1 to i64
llvm-svn: 206437
| -rw-r--r-- | llvm/lib/Target/R600/SIISelLowering.cpp | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/R600/uaddo.ll | 17 | ||||
| -rw-r--r-- | llvm/test/CodeGen/R600/zero_extend.ll | 11 |
3 files changed, 34 insertions, 2 deletions
diff --git a/llvm/lib/Target/R600/SIISelLowering.cpp b/llvm/lib/Target/R600/SIISelLowering.cpp index 175709cad6d..235665ab89e 100644 --- a/llvm/lib/Target/R600/SIISelLowering.cpp +++ b/llvm/lib/Target/R600/SIISelLowering.cpp @@ -972,8 +972,12 @@ SDValue SITargetLowering::LowerZERO_EXTEND(SDValue Op, return SDValue(); } - return DAG.getNode(ISD::BUILD_PAIR, DL, VT, Op.getOperand(0), - DAG.getConstant(0, MVT::i32)); + SDValue Src = Op.getOperand(0); + if (Src.getValueType() != MVT::i32) + Src = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Src); + + SDValue Zero = DAG.getConstant(0, MVT::i32); + return DAG.getNode(ISD::BUILD_PAIR, DL, VT, Src, Zero); } //===----------------------------------------------------------------------===// diff --git a/llvm/test/CodeGen/R600/uaddo.ll b/llvm/test/CodeGen/R600/uaddo.ll new file mode 100644 index 00000000000..4f24c85f1a0 --- /dev/null +++ b/llvm/test/CodeGen/R600/uaddo.ll @@ -0,0 +1,17 @@ +; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s + +declare { i64, i1 } @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone + +; SI-LABEL: @uaddo_i64_zext +; SI: ADD +; SI: ADDC +; SI: ADDC +define void @uaddo_i64_zext(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind { + %uadd = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b) nounwind + %val = extractvalue { i64, i1 } %uadd, 0 + %carry = extractvalue { i64, i1 } %uadd, 1 + %ext = zext i1 %carry to i64 + %add2 = add i64 %val, %ext + store i64 %add2, i64 addrspace(1)* %out, align 8 + ret void +} diff --git a/llvm/test/CodeGen/R600/zero_extend.ll b/llvm/test/CodeGen/R600/zero_extend.ll index a114bfc4a02..c561ff7428e 100644 --- a/llvm/test/CodeGen/R600/zero_extend.ll +++ b/llvm/test/CodeGen/R600/zero_extend.ll @@ -26,3 +26,14 @@ entry: store i32 %1, i32 addrspace(1)* %out ret void } + +; SI-CHECK-LABEL: @zext_i1_to_i64 +; SI-CHECK: V_CMP_EQ_I32 +; SI-CHECK: V_CNDMASK_B32 +; SI-CHECK: V_MOV_B32_e32 v{{[0-9]+}}, 0 +define void @zext_i1_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) nounwind { + %cmp = icmp eq i32 %a, %b + %ext = zext i1 %cmp to i64 + store i64 %ext, i64 addrspace(1)* %out, align 8 + ret void +} |
