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| author | Robert Wilhelm <robert.wilhelm@gmx.net> | 2013-09-14 09:34:24 +0000 |
|---|---|---|
| committer | Robert Wilhelm <robert.wilhelm@gmx.net> | 2013-09-14 09:34:24 +0000 |
| commit | 516be56fd94f9d65e23a2792045071e72039df74 (patch) | |
| tree | a73c8f5248a18e0e924d7a2d09708a115f82fc25 | |
| parent | ebeac5cb89aa0fca23abe203e4714218c8b4ee7c (diff) | |
| download | bcm5719-llvm-516be56fd94f9d65e23a2792045071e72039df74.tar.gz bcm5719-llvm-516be56fd94f9d65e23a2792045071e72039df74.zip | |
Fix spelling.
llvm-svn: 190749
| -rw-r--r-- | llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index 696d039e74e..321c3f4b029 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -4201,7 +4201,7 @@ breakPartialRegDependency(MachineBasicBlock::iterator MI, // FIXME: In some cases, VLDRS can be changed to a VLD1DUPd32 which defines // the full D-register by loading the same value to both lanes. The // instruction is micro-coded with 2 uops, so don't do this until we can - // properly schedule micro-coded instuctions. The dispatcher stalls cause + // properly schedule micro-coded instructions. The dispatcher stalls cause // too big regressions. // Insert the dependency-breaking FCONSTD before MI. |
