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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-06-01 14:38:02 +0000 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-06-01 14:38:02 +0000 |
commit | 50f43e4168dff15519532240de5afdbb07d4b8b7 (patch) | |
tree | 0603b217846ee5c607ffd98d897f9319c523d198 | |
parent | 94eb633dd2966ae5b7f8bd480c903030d1613730 (diff) | |
download | bcm5719-llvm-50f43e4168dff15519532240de5afdbb07d4b8b7.tar.gz bcm5719-llvm-50f43e4168dff15519532240de5afdbb07d4b8b7.zip |
AMDGPU: Set high getCSRFirstUseCost
llvm-svn: 304416
-rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h index b91cdddc552..a648c178101 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h @@ -66,6 +66,12 @@ public: const uint32_t *getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override; + // Stack access is very expensive. CSRs are also the high registers, and we + // want to minimize the number of used registers. + unsigned getCSRFirstUseCost() const override { + return 100; + } + unsigned getFrameRegister(const MachineFunction &MF) const override; bool requiresRegisterScavenging(const MachineFunction &Fn) const override; |