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authorAhmed Bougacha <ahmed.bougacha@gmail.com>2017-02-23 23:57:36 +0000
committerAhmed Bougacha <ahmed.bougacha@gmail.com>2017-02-23 23:57:36 +0000
commit4f8dd0202dd32881fe55a13bb768efbd2c9c0888 (patch)
treee12f57f84e2af29123101259cb96c285d0712e0f
parenteceabddcfd6ad653ee1acdcdd2b712343227d133 (diff)
downloadbcm5719-llvm-4f8dd0202dd32881fe55a13bb768efbd2c9c0888.tar.gz
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[GlobalISel] Don't translate other blocks when one failed.
We were stopping the translation of the parent block when the translation of an instruction failed, but we were still trying to translate the other blocks of the parent function. Don't do that. llvm-svn: 296047
-rw-r--r--llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp68
1 files changed, 33 insertions, 35 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index c94e2955a1a..6b93a121ce3 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -1076,45 +1076,43 @@ bool IRTranslator::runOnMachineFunction(MachineFunction &CurMF) {
R << "unable to translate instruction: " << ore::NV("Opcode", &Inst)
<< ": '" << InstStr.str() << "'";
reportTranslationError(*MF, *TPC, *ORE, R);
- break;
+ return false;
}
}
}
- if (Succeeded) {
- finishPendingPhis();
-
- // Now that the MachineFrameInfo has been configured, no further changes to
- // the reserved registers are possible.
- MRI->freezeReservedRegs(*MF);
-
- // Merge the argument lowering and constants block with its single
- // successor, the LLVM-IR entry block. We want the basic block to
- // be maximal.
- assert(EntryBB->succ_size() == 1 &&
- "Custom BB used for lowering should have only one successor");
- // Get the successor of the current entry block.
- MachineBasicBlock &NewEntryBB = **EntryBB->succ_begin();
- assert(NewEntryBB.pred_size() == 1 &&
- "LLVM-IR entry block has a predecessor!?");
- // Move all the instruction from the current entry block to the
- // new entry block.
- NewEntryBB.splice(NewEntryBB.begin(), EntryBB, EntryBB->begin(),
- EntryBB->end());
-
- // Update the live-in information for the new entry block.
- for (const MachineBasicBlock::RegisterMaskPair &LiveIn : EntryBB->liveins())
- NewEntryBB.addLiveIn(LiveIn);
- NewEntryBB.sortUniqueLiveIns();
-
- // Get rid of the now empty basic block.
- EntryBB->removeSuccessor(&NewEntryBB);
- MF->remove(EntryBB);
- MF->DeleteMachineBasicBlock(EntryBB);
-
- assert(&MF->front() == &NewEntryBB &&
- "New entry wasn't next in the list of basic block!");
- }
+ finishPendingPhis();
+
+ // Now that the MachineFrameInfo has been configured, no further changes to
+ // the reserved registers are possible.
+ MRI->freezeReservedRegs(*MF);
+
+ // Merge the argument lowering and constants block with its single
+ // successor, the LLVM-IR entry block. We want the basic block to
+ // be maximal.
+ assert(EntryBB->succ_size() == 1 &&
+ "Custom BB used for lowering should have only one successor");
+ // Get the successor of the current entry block.
+ MachineBasicBlock &NewEntryBB = **EntryBB->succ_begin();
+ assert(NewEntryBB.pred_size() == 1 &&
+ "LLVM-IR entry block has a predecessor!?");
+ // Move all the instruction from the current entry block to the
+ // new entry block.
+ NewEntryBB.splice(NewEntryBB.begin(), EntryBB, EntryBB->begin(),
+ EntryBB->end());
+
+ // Update the live-in information for the new entry block.
+ for (const MachineBasicBlock::RegisterMaskPair &LiveIn : EntryBB->liveins())
+ NewEntryBB.addLiveIn(LiveIn);
+ NewEntryBB.sortUniqueLiveIns();
+
+ // Get rid of the now empty basic block.
+ EntryBB->removeSuccessor(&NewEntryBB);
+ MF->remove(EntryBB);
+ MF->DeleteMachineBasicBlock(EntryBB);
+
+ assert(&MF->front() == &NewEntryBB &&
+ "New entry wasn't next in the list of basic block!");
return false;
}
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