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authorZhan Jun Liau <zhanjunl@ca.ibm.com>2016-06-27 15:55:30 +0000
committerZhan Jun Liau <zhanjunl@ca.ibm.com>2016-06-27 15:55:30 +0000
commit4f130b4410b2662e9adb1947cd402d9593409c21 (patch)
tree5d3420d855e7dbf75b02fdf7a984db6348731b34
parent02478f416639e1e322df34c139cd90874dcfb2c1 (diff)
downloadbcm5719-llvm-4f130b4410b2662e9adb1947cd402d9593409c21.tar.gz
bcm5719-llvm-4f130b4410b2662e9adb1947cd402d9593409c21.zip
[SystemZ] Avoid generating 2 XOR instructions for (and (xor x, -1), y)
Summary: Created a pattern to match 64-bit mode (and (xor x, -1), y) to a shorter sequence of instructions. Before the change, the canonical form is translated to: xihf %r3, 4294967295 xilf %r3, 4294967295 ngr %r2, %r3 After the change, the canonical form is translated to: ngr %r3, %r2 xgr %r2, %r3 Reviewers: zhanjunl, uweigand Subscribers: llvm-commits Author: assem Committing on behalf of Assem. Differential Revision: http://reviews.llvm.org/D21693 llvm-svn: 273887
-rw-r--r--llvm/lib/Target/SystemZ/SystemZInstrInfo.td5
-rw-r--r--llvm/test/CodeGen/SystemZ/and-xor-01.ll14
2 files changed, 19 insertions, 0 deletions
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
index 77a9fdd4add..7a7a3e30863 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -1680,6 +1680,11 @@ def : Pat<(sra (shl (i64 (anyext (i32 (z_select_ccmask 1, 0, imm32zx4:$valid,
(i32 63)),
(Select64 (LGHI -1), (LGHI 0), imm32zx4:$valid, imm32zx4:$cc)>;
+// Avoid generating 2 XOR instructions. (xor (and x, y), y) is
+// equivalent to (and (xor x, -1), y)
+def : Pat<(and (xor GR64:$x, (i64 -1)), GR64:$y),
+ (XGR GR64:$y, (NGR GR64:$y, GR64:$x))>;
+
// Peepholes for turning scalar operations into block operations.
defm : BlockLoadStore<anyextloadi8, i32, MVCSequence, NCSequence, OCSequence,
XCSequence, 1>;
diff --git a/llvm/test/CodeGen/SystemZ/and-xor-01.ll b/llvm/test/CodeGen/SystemZ/and-xor-01.ll
new file mode 100644
index 00000000000..f29c7d576d9
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/and-xor-01.ll
@@ -0,0 +1,14 @@
+; Testing peephole for generating shorter code for (and (xor b, -1), a)
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+define i64 @f1(i64 %a, i64 %b) {
+; CHECK-LABEL: f1:
+; CHECK: ngr %r3, %r2
+; CHECK: xgr %r2, %r3
+; CHECK: br %r14
+ %neg = xor i64 %b, -1
+ %and = and i64 %neg, %a
+ ret i64 %and
+}
+
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