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| author | Martin Storsjo <martin@martin.st> | 2019-05-20 19:53:28 +0000 |
|---|---|---|
| committer | Martin Storsjo <martin@martin.st> | 2019-05-20 19:53:28 +0000 |
| commit | 4ed18e5ef5212b208d8707c08cc3c7f16ce2738d (patch) | |
| tree | 6ffb5b39b16348080d8768a6ff2d910e3376a115 | |
| parent | 80efcdcdf882429e173a0da28f5edf8987dd1b08 (diff) | |
| download | bcm5719-llvm-4ed18e5ef5212b208d8707c08cc3c7f16ce2738d.tar.gz bcm5719-llvm-4ed18e5ef5212b208d8707c08cc3c7f16ce2738d.zip | |
[AArch64] Handle lowering lround on windows, where long is 32 bit
Differential Revision: https://reviews.llvm.org/D62108
llvm-svn: 361192
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrInfo.td | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/lround-conv-win.ll | 44 |
2 files changed, 48 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index bf6be6761a9..f426da4f1c8 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -3083,6 +3083,10 @@ defm : FPToIntegerPats<fp_to_uint, ftrunc, "FCVTZU">; defm : FPToIntegerPats<fp_to_sint, fround, "FCVTAS">; defm : FPToIntegerPats<fp_to_uint, fround, "FCVTAU">; +def : Pat<(i32 (lround f32:$Rn)), + (!cast<Instruction>(FCVTASUWSr) f32:$Rn)>; +def : Pat<(i32 (lround f64:$Rn)), + (!cast<Instruction>(FCVTASUWDr) f64:$Rn)>; def : Pat<(i64 (lround f32:$Rn)), (!cast<Instruction>(FCVTASUXSr) f32:$Rn)>; def : Pat<(i64 (lround f64:$Rn)), diff --git a/llvm/test/CodeGen/AArch64/lround-conv-win.ll b/llvm/test/CodeGen/AArch64/lround-conv-win.ll new file mode 100644 index 00000000000..8bc9213fdce --- /dev/null +++ b/llvm/test/CodeGen/AArch64/lround-conv-win.ll @@ -0,0 +1,44 @@ +; RUN: llc < %s -mtriple=aarch64-windows -mattr=+neon | FileCheck %s + +; CHECK-LABEL: testmsxs: +; CHECK: fcvtas w8, s0 +; CHECK-NEXT: sxtw x0, w8 +; CHECK-NEXT: ret +define i64 @testmsxs(float %x) { +entry: + %0 = tail call i32 @llvm.lround.i32.f32(float %x) + %conv = sext i32 %0 to i64 + ret i64 %conv +} + +; CHECK-LABEL: testmsws: +; CHECK: fcvtas w0, s0 +; CHECK-NEXT: ret +define i32 @testmsws(float %x) { +entry: + %0 = tail call i32 @llvm.lround.i32.f32(float %x) + ret i32 %0 +} + +; CHECK-LABEL: testmsxd: +; CHECK: fcvtas w8, d0 +; CHECK-NEXT: sxtw x0, w8 +; CHECK-NEXT: ret +define i64 @testmsxd(double %x) { +entry: + %0 = tail call i32 @llvm.lround.i32.f64(double %x) + %conv = sext i32 %0 to i64 + ret i64 %conv +} + +; CHECK-LABEL: testmswd: +; CHECK: fcvtas w0, d0 +; CHECK-NEXT: ret +define i32 @testmswd(double %x) { +entry: + %0 = tail call i32 @llvm.lround.i32.f64(double %x) + ret i32 %0 +} + +declare i32 @llvm.lround.i32.f32(float) nounwind readnone +declare i32 @llvm.lround.i32.f64(double) nounwind readnone |
