summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorJohnny Chen <johnny.chen@apple.com>2010-04-09 21:01:02 +0000
committerJohnny Chen <johnny.chen@apple.com>2010-04-09 21:01:02 +0000
commit4e8bd580016762cde37efc415044e56f5dc332e8 (patch)
treebff08ad531207bf8fa1f048e5bd44b5f928044e1
parent74e2ef68b9791dbad58c0dcea83358d715503230 (diff)
downloadbcm5719-llvm-4e8bd580016762cde37efc415044e56f5dc332e8.tar.gz
bcm5719-llvm-4e8bd580016762cde37efc415044e56f5dc332e8.zip
If all the bit positions are not specified; do not decode the instructions.
We are bound to fail! For proper disassembly, the well-known encoding bits of the instruction must be fully specified. This also removes pseudo instructions from considerations of disassembly, which is a better design and less fragile than the name matchings. llvm-svn: 100899
-rw-r--r--llvm/utils/TableGen/ARMDecoderEmitter.cpp19
-rw-r--r--llvm/utils/TableGen/Record.h5
2 files changed, 15 insertions, 9 deletions
diff --git a/llvm/utils/TableGen/ARMDecoderEmitter.cpp b/llvm/utils/TableGen/ARMDecoderEmitter.cpp
index 9e8555c4f07..0bb55ce9f3f 100644
--- a/llvm/utils/TableGen/ARMDecoderEmitter.cpp
+++ b/llvm/utils/TableGen/ARMDecoderEmitter.cpp
@@ -1550,6 +1550,16 @@ bool ARMDecoderEmitter::ARMDEBackend::populateInstruction(
const StringRef Name = Def.getName();
uint8_t Form = getByteField(Def, "Form");
+ BitsInit &Bits = getBitsField(Def, "Inst");
+
+ // If all the bit positions are not specified; do not decode this instruction.
+ // We are bound to fail! For proper disassembly, the well-known encoding bits
+ // of the instruction must be fully specified.
+ //
+ // This also removes pseudo instructions from considerations of disassembly,
+ // which is a better design and less fragile than the name matchings.
+ if (Bits.allInComplete()) return false;
+
if (TN == TARGET_ARM) {
// FIXME: what about Int_MemBarrierV6 and Int_SyncBarrierV6?
if ((Name != "Int_MemBarrierV7" && Name != "Int_SyncBarrierV7") &&
@@ -1670,13 +1680,6 @@ bool ARMDecoderEmitter::ARMDEBackend::populateInstruction(
if (!thumbInstruction(Form))
return false;
- // Ignore pseudo instructions.
- if (Name == "tInt_eh_sjlj_setjmp" || Name == "t2Int_eh_sjlj_setjmp" ||
- Name == "tInt_eh_sjlj_setjmp_nofp" ||
- Name == "t2Int_eh_sjlj_setjmp_nofp" ||
- Name == "t2MOVi32imm" || Name == "tBX" || Name == "tBXr9")
- return false;
-
// On Darwin R9 is call-clobbered. Ignore the non-Darwin counterparts.
if (Name == "tBL" || Name == "tBLXi" || Name == "tBLXr")
return false;
@@ -1741,8 +1744,6 @@ bool ARMDecoderEmitter::ARMDEBackend::populateInstruction(
}
DEBUG({
- BitsInit &Bits = getBitsField(Def, "Inst");
-
errs() << " ";
// Dumps the instruction encoding bits.
diff --git a/llvm/utils/TableGen/Record.h b/llvm/utils/TableGen/Record.h
index 55c1a80f9b6..576d626e069 100644
--- a/llvm/utils/TableGen/Record.h
+++ b/llvm/utils/TableGen/Record.h
@@ -609,6 +609,11 @@ public:
if (!getBit(i)->isComplete()) return false;
return true;
}
+ bool allInComplete() const {
+ for (unsigned i = 0; i != getNumBits(); ++i)
+ if (getBit(i)->isComplete()) return false;
+ return true;
+ }
virtual std::string getAsString() const;
virtual Init *resolveReferences(Record &R, const RecordVal *RV);
OpenPOWER on IntegriCloud