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| author | Luke Geeson <luke.geeson@arm.com> | 2018-08-13 08:37:41 +0000 |
|---|---|---|
| committer | Luke Geeson <luke.geeson@arm.com> | 2018-08-13 08:37:41 +0000 |
| commit | 4ce41d2bb71108ec7603cd1217310923b103e059 (patch) | |
| tree | 0cd05ad962ff203b78be46357099a550707c617e | |
| parent | a9c9d000162b2c54a11091a42fe67e28ef32995d (diff) | |
| download | bcm5719-llvm-4ce41d2bb71108ec7603cd1217310923b103e059.tar.gz bcm5719-llvm-4ce41d2bb71108ec7603cd1217310923b103e059.zip | |
[ARM] Added FP16 VREV Vector Instrinsic CodeGen support
llvm-svn: 339546
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrNEON.td | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll | 24 |
2 files changed, 13 insertions, 13 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td index 7f2ebcd7b62..5a300c727bb 100644 --- a/llvm/lib/Target/ARM/ARMInstrNEON.td +++ b/llvm/lib/Target/ARM/ARMInstrNEON.td @@ -6589,6 +6589,8 @@ def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>; def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>; def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>; def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>; +def : Pat<(v8f16 (NEONvrev64 (v8f16 QPR:$Vm))), (VREV64q16 QPR:$Vm)>; +def : Pat<(v4f16 (NEONvrev64 (v4f16 DPR:$Vm))), (VREV64d16 DPR:$Vm)>; // VREV32 : Vector Reverse elements within 32-bit words diff --git a/llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll b/llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll index dc0f4a99848..a9c5838f104 100644 --- a/llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll +++ b/llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll @@ -1213,19 +1213,17 @@ entry: ret <8 x half> %vext } -; FIXME (PR38404) -; -;define dso_local <4 x half> @test_vrev64_f16(<4 x half> %a) { -;entry: -; %shuffle.i = shufflevector <4 x half> %a, <4 x half> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> -; ret <4 x half> %shuffle.i -;} -; -;define dso_local <8 x half> @test_vrev64q_f16(<8 x half> %a) { -;entry: -; %shuffle.i = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> -; ret <8 x half> %shuffle.i -;} +define dso_local <4 x half> @test_vrev64_f16(<4 x half> %a) { +entry: + %shuffle.i = shufflevector <4 x half> %a, <4 x half> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> + ret <4 x half> %shuffle.i +} + +define dso_local <8 x half> @test_vrev64q_f16(<8 x half> %a) { +entry: + %shuffle.i = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> + ret <8 x half> %shuffle.i +} declare <4 x half> @llvm.fabs.v4f16(<4 x half>) declare <8 x half> @llvm.fabs.v8f16(<8 x half>) |
