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| author | Arnold Schwaighofer <aschwaighofer@apple.com> | 2015-07-07 18:31:55 +0000 |
|---|---|---|
| committer | Arnold Schwaighofer <aschwaighofer@apple.com> | 2015-07-07 18:31:55 +0000 |
| commit | 4bc34b1515ee215c1795d5cdb3409d5e905473a8 (patch) | |
| tree | 2d8a3d621118ee687b1196258a2de5b93ef2cf49 | |
| parent | 42e9f967127e5efea4c3b8638c9c4da8ad885fba (diff) | |
| download | bcm5719-llvm-4bc34b1515ee215c1795d5cdb3409d5e905473a8.tar.gz bcm5719-llvm-4bc34b1515ee215c1795d5cdb3409d5e905473a8.zip | |
Add a pattern for a nvcast from v2f64 -> v4f32
Since the NvCast is generated by the selection process the concerns about
endianess and bit reversal don't apply.
rdar://21703486
llvm-svn: 241611
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrInfo.td | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/arm64-nvcast.ll | 8 |
2 files changed, 9 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index b73e0958df9..0572619d00c 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -5315,6 +5315,7 @@ def : Pat<(v8i16 (AArch64NvCast (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>; def : Pat<(v4i32 (AArch64NvCast (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>; def : Pat<(v2i64 (AArch64NvCast (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>; def : Pat<(v2f64 (AArch64NvCast (v2f64 FPR128:$src))), (v2f64 FPR128:$src)>; +def : Pat<(v4f32 (AArch64NvCast (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>; let Predicates = [IsLE] in { def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; diff --git a/llvm/test/CodeGen/AArch64/arm64-nvcast.ll b/llvm/test/CodeGen/AArch64/arm64-nvcast.ll new file mode 100644 index 00000000000..452f6a6dee6 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/arm64-nvcast.ll @@ -0,0 +1,8 @@ +; RUN: llc < %s -mtriple=arm64-apple-ios + +define void @test(float * %p1, i32 %v1) { +entry: + %v2 = extractelement <3 x float> <float 0.000000e+00, float 2.000000e+00, float 0.000000e+00>, i32 %v1 + store float %v2, float* %p1, align 4 + ret void +} |
