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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2015-03-17 14:37:39 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2015-03-17 14:37:39 +0000 |
| commit | 49f643c4723e1f0ceb050ea01d18afd8a1590636 (patch) | |
| tree | 9e86104780361270dd6f01aba2d772646f183374 | |
| parent | ec8da3de019fa2b30968b1877acb56ec2ab368a7 (diff) | |
| download | bcm5719-llvm-49f643c4723e1f0ceb050ea01d18afd8a1590636.tar.gz bcm5719-llvm-49f643c4723e1f0ceb050ea01d18afd8a1590636.zip | |
Re-commit: [hexagon] Distinguish the 'o', 'v', and 'm' inline assembly memory constraints.
Summary:
But still handle them the same way since I don't know how they differ on
this target.
No functional change intended.
Reviewers: kparzysz, adasgupt
Reviewed By: kparzysz, adasgupt
Subscribers: colinl, llvm-commits
Differential Revision: http://reviews.llvm.org/D8204
Like for the PowerPC target, I've had to add 'i' to the constraint mappings in
order to pass 2007-12-17-InvokeAsm.ll. It's not clear why 'i' has historically
been treated as a memory constraint.
llvm-svn: 232480
| -rw-r--r-- | llvm/include/llvm/IR/InlineAsm.h | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp | 7 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonISelLowering.h | 7 |
3 files changed, 10 insertions, 6 deletions
diff --git a/llvm/include/llvm/IR/InlineAsm.h b/llvm/include/llvm/IR/InlineAsm.h index a1d72a4af73..bdb75dbc5b2 100644 --- a/llvm/include/llvm/IR/InlineAsm.h +++ b/llvm/include/llvm/IR/InlineAsm.h @@ -243,7 +243,7 @@ public: Constraint_i, Constraint_m, Constraint_o, - Constraint_v, // Unused at the moment since Constraint_m is always used. + Constraint_v, Constraint_Q, Constraint_Z, Constraint_Zy, diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index 795faf97af4..33c4ce51aac 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -1108,11 +1108,12 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, SDValue Inp = Op, Res; switch (ConstraintID) { - case InlineAsm::Constraint_o: // Offsetable. - case InlineAsm::Constraint_v: // Not offsetable. default: return true; - case InlineAsm::Constraint_m: // Memory. + case InlineAsm::Constraint_i: + case InlineAsm::Constraint_o: // Offsetable. + case InlineAsm::Constraint_v: // Not offsetable. + case InlineAsm::Constraint_m: // Memory. if (SelectAddrFI(Inp, Res)) OutOps.push_back(Res); else diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h index 7b772f07eb0..99214c8d445 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h @@ -185,8 +185,11 @@ bool isPositiveHalfWord(SDNode *N); unsigned getInlineAsmMemConstraint( const std::string &ConstraintCode) const override { - // FIXME: Map different constraints differently. - return InlineAsm::Constraint_m; + if (ConstraintCode == "o") + return InlineAsm::Constraint_o; + else if (ConstraintCode == "v") + return InlineAsm::Constraint_v; + return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); } // Intrinsics |
