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| author | Hal Finkel <hfinkel@anl.gov> | 2013-07-11 17:43:32 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-07-11 17:43:32 +0000 |
| commit | 4715081787d4c3f1e2fa4b8d23b484b5b5d437bb (patch) | |
| tree | dc5ec2dcd59005da43b65d8b551751aab9d5f96d | |
| parent | 3095993d6f4d062771083f4258fd2a5a35925c13 (diff) | |
| download | bcm5719-llvm-4715081787d4c3f1e2fa4b8d23b484b5b5d437bb.tar.gz bcm5719-llvm-4715081787d4c3f1e2fa4b8d23b484b5b5d437bb.zip | |
PPC: Add some missing V_SET0 patterns
We had patterns to match v4i32 immAllZerosV -> V_SET0, but not patterns for
v8i16 (which occurs in the test case) or v16i8. The same was true for
V_SETALLONES (so I added the associated patterns for those as well).
Another bug found by llvm-stress.
llvm-svn: 186108
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrAltivec.td | 17 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/set0-v8i16.ll | 18 |
2 files changed, 33 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td index 09765597a26..fdea51d51a2 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td +++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td @@ -665,11 +665,24 @@ def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>; def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>; let isCodeGenOnly = 1 in { -def V_SET0 : VXForm_setzero<1220, (outs vrrc:$vD), (ins), +def V_SET0B : VXForm_setzero<1220, (outs vrrc:$vD), (ins), + "vxor $vD, $vD, $vD", VecFP, + [(set v16i8:$vD, (v16i8 immAllZerosV))]>; +def V_SET0H : VXForm_setzero<1220, (outs vrrc:$vD), (ins), + "vxor $vD, $vD, $vD", VecFP, + [(set v8i16:$vD, (v8i16 immAllZerosV))]>; +def V_SET0 : VXForm_setzero<1220, (outs vrrc:$vD), (ins), "vxor $vD, $vD, $vD", VecFP, [(set v4i32:$vD, (v4i32 immAllZerosV))]>; + let IMM=-1 in { -def V_SETALLONES : VXForm_3<908, (outs vrrc:$vD), (ins), +def V_SETALLONESB : VXForm_3<908, (outs vrrc:$vD), (ins), + "vspltisw $vD, -1", VecFP, + [(set v16i8:$vD, (v16i8 immAllOnesV))]>; +def V_SETALLONESH : VXForm_3<908, (outs vrrc:$vD), (ins), + "vspltisw $vD, -1", VecFP, + [(set v8i16:$vD, (v8i16 immAllOnesV))]>; +def V_SETALLONES : VXForm_3<908, (outs vrrc:$vD), (ins), "vspltisw $vD, -1", VecFP, [(set v4i32:$vD, (v4i32 immAllOnesV))]>; } diff --git a/llvm/test/CodeGen/PowerPC/set0-v8i16.ll b/llvm/test/CodeGen/PowerPC/set0-v8i16.ll new file mode 100644 index 00000000000..13d51dfc8e4 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/set0-v8i16.ll @@ -0,0 +1,18 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s +target triple = "powerpc64-unknown-linux-gnu" + +define void @autogen_SD367951() { +BB: + %Shuff = shufflevector <16 x i16> zeroinitializer, <16 x i16> zeroinitializer, <16 x i32> <i32 26, i32 28, i32 30, i32 undef, i32 2, i32 4, i32 undef, i32 undef, i32 10, i32 undef, i32 14, i32 16, i32 undef, i32 20, i32 undef, i32 24> + %Shuff7 = shufflevector <16 x i16> zeroinitializer, <16 x i16> %Shuff, <16 x i32> <i32 20, i32 undef, i32 24, i32 26, i32 28, i32 undef, i32 0, i32 undef, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18> + %Cmp11 = icmp ugt <16 x i16> %Shuff7, zeroinitializer + %E27 = extractelement <16 x i1> %Cmp11, i32 5 + br label %CF76 + +CF76: ; preds = %CF80, %CF76, %BB + br i1 undef, label %CF76, label %CF80 + +CF80: ; preds = %CF76 + %Sl37 = select i1 %E27, <16 x i16> undef, <16 x i16> %Shuff + br label %CF76 +} |
