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| author | Colin LeMahieu <colinl@codeaurora.org> | 2014-12-16 16:27:17 +0000 |
|---|---|---|
| committer | Colin LeMahieu <colinl@codeaurora.org> | 2014-12-16 16:27:17 +0000 |
| commit | 455f24aa7720391a475670aeb9a6ed0950a6d336 (patch) | |
| tree | 57968c26abe52f5fd765e44475ceb2f5b925c546 | |
| parent | d60fe11919e502d059118aeb179b4a611314bf8e (diff) | |
| download | bcm5719-llvm-455f24aa7720391a475670aeb9a6ed0950a6d336.tar.gz bcm5719-llvm-455f24aa7720391a475670aeb9a6ed0950a6d336.zip | |
[Hexagon] Adding saturate and swizzle instructions.
llvm-svn: 224343
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonInstrInfo.td | 22 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/Hexagon/xtype_perm.txt | 14 |
2 files changed, 36 insertions, 0 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td index 79ca41bdee5..b5711c27fee 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td @@ -2710,6 +2710,14 @@ class T_S2op_1 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut, class T_S2op_1_di <string mnemonic, bits<2> MajOp, bits<3> MinOp> : T_S2op_1 <mnemonic, 0b0100, DoubleRegs, IntRegs, MajOp, MinOp, 0>; +let hasNewValue = 1 in +class T_S2op_1_id <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0> + : T_S2op_1 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, isSat>; + +let hasNewValue = 1 in +class T_S2op_1_ii <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0> + : T_S2op_1 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp, isSat>; + // Sign extend word to doubleword let isCodeGenOnly = 0 in def A2_sxtw : T_S2op_1_di <"sxtw", 0b01, 0b000>; @@ -2720,6 +2728,20 @@ def: Pat <(i64 (sext I32:$src)), (A2_sxtw I32:$src)>; // STYPE/ALU - //===----------------------------------------------------------------------===// + +// Swizzle the bytes of a word +let isCodeGenOnly = 0 in +def A2_swiz : T_S2op_1_ii <"swiz", 0b10, 0b111>; + +// Saturate +let Defs = [USR_OVF], isCodeGenOnly = 0 in { + def A2_sat : T_S2op_1_id <"sat", 0b11, 0b000>; + def A2_satb : T_S2op_1_ii <"satb", 0b11, 0b111>; + def A2_satub : T_S2op_1_ii <"satub", 0b11, 0b110>; + def A2_sath : T_S2op_1_ii <"sath", 0b11, 0b100>; + def A2_satuh : T_S2op_1_ii <"satuh", 0b11, 0b101>; +} + //===----------------------------------------------------------------------===// // STYPE/BIT + //===----------------------------------------------------------------------===// diff --git a/llvm/test/MC/Disassembler/Hexagon/xtype_perm.txt b/llvm/test/MC/Disassembler/Hexagon/xtype_perm.txt new file mode 100644 index 00000000000..1de3d11d820 --- /dev/null +++ b/llvm/test/MC/Disassembler/Hexagon/xtype_perm.txt @@ -0,0 +1,14 @@ +# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s + +0x11 0xc0 0xd4 0x88 +# CHECK: r17 = sat(r21:20) +0x91 0xc0 0xd5 0x8c +# CHECK: r17 = sath(r21) +0xb1 0xc0 0xd5 0x8c +# CHECK: r17 = satuh(r21) +0xd1 0xc0 0xd5 0x8c +# CHECK: r17 = satub(r21) +0xf1 0xc0 0xd5 0x8c +# CHECK: r17 = satb(r21) +0xf1 0xc0 0x95 0x8c +# CHECK: r17 = swiz(r21) |
