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| author | Craig Topper <craig.topper@intel.com> | 2018-03-23 19:15:05 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-03-23 19:15:05 +0000 |
| commit | 4529d3abcb0f3512d61516af5d7618f48b4b03c4 (patch) | |
| tree | ee1fb0e249ed26ec73e1d5b16d388dcfa3e8c4f0 | |
| parent | 02fb3907f1c0e8d17e3e123345a79bf5bd74ac84 (diff) | |
| download | bcm5719-llvm-4529d3abcb0f3512d61516af5d7618f48b4b03c4.tar.gz bcm5719-llvm-4529d3abcb0f3512d61516af5d7618f48b4b03c4.zip | |
[X86] Add itinerary to RCPSS*_Int and similar instructions.
llvm-svn: 328353
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSSE.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index 1963425e236..2057a8d685e 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -3198,12 +3198,12 @@ multiclass avx_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC, def r_Int : I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), - []>, Sched<[itins.Sched.Folded]>; + [], itins.rr>, Sched<[itins.Sched.Folded]>; let mayLoad = 1 in def m_Int : I<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, intmemop:$src2), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), - []>, Sched<[itins.Sched.Folded, ReadAfterLd]>; + [], itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>; } } |

