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| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-06-29 13:35:05 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-06-29 13:35:05 +0000 |
| commit | 4401049f05b94b7df9117e4aea895e5a3721ffa5 (patch) | |
| tree | a3ebb7ef95e39b659e9452cdc616df55c95a6e27 | |
| parent | d0a2f0f95a9cb9ed21bd1a655482b147b8fc3768 (diff) | |
| download | bcm5719-llvm-4401049f05b94b7df9117e4aea895e5a3721ffa5.tar.gz bcm5719-llvm-4401049f05b94b7df9117e4aea895e5a3721ffa5.zip | |
thinko
llvm-svn: 22309
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaISelPattern.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp index 1cb07f1e6b7..6cba016e683 100644 --- a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp @@ -1819,6 +1819,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) { Tmp2 = SelectExpr(N.getOperand(1)); BuildMI(BB, DestType == MVT::f64 ? Alpha::DIVT : Alpha::DIVS, 2, Result) .addReg(Tmp1).addReg(Tmp2); + return Result; } else { ConstantSDNode* CSD; //check if we can convert into a shift! |
