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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-12-24 05:14:55 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-12-24 05:14:55 +0000 |
| commit | 4339b3ff3543a7c715a2d58210c7a0cb0521deef (patch) | |
| tree | 9ad2ea3be5064827ec067c7d3dcacfe3366d9809 | |
| parent | 95cc9d5f14eb4e76d38c312f2473a3d28d140a35 (diff) | |
| download | bcm5719-llvm-4339b3ff3543a7c715a2d58210c7a0cb0521deef.tar.gz bcm5719-llvm-4339b3ff3543a7c715a2d58210c7a0cb0521deef.zip | |
AMDGPU: Fix getRegisterBitWidth for vectors
llvm-svn: 256362
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp index c20a66e4481..54a003d6a9c 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp @@ -74,7 +74,9 @@ unsigned AMDGPUTTIImpl::getNumberOfRegisters(bool Vec) { return 4 * 128; // XXX - 4 channels. Should these count as vector instead? } -unsigned AMDGPUTTIImpl::getRegisterBitWidth(bool) { return 32; } +unsigned AMDGPUTTIImpl::getRegisterBitWidth(bool Vector) { + return Vector ? 0 : 32; +} unsigned AMDGPUTTIImpl::getMaxInterleaveFactor(unsigned VF) { // Semi-arbitrary large amount. |
