[X86][MPX] Tag MPX instructions scheduler classes

Currently tagged these as system instructions, once we have uses for them (ASAN?) and they are faster we will need to improve on this.

llvm-svn: 320173

2 files changed, 19 insertions, 14 deletions

diff --git a/llvm/lib/Target/X86/X86InstrMPX.td b/llvm/lib/Target/X86/X86InstrMPX.td
index 104ba2a174d..9d6bcba9f91 100644
--- a/llvm/lib/Target/X86/X86InstrMPX.td
+++ b/llvm/lib/Target/X86/X86InstrMPX.td
@@ -13,13 +13,16 @@
 //
 //===----------------------------------------------------------------------===//
 
+// FIXME: Investigate a better scheduler itinerary once MPX is used inside LLVM.
+let SchedRW = [WriteSystem] in {
+
 multiclass mpx_bound_make<bits<8> opc, string OpcodeStr> {
 let mayLoad = 1 in {
   def 32rm: I<opc, MRMSrcMem, (outs BNDR:$dst), (ins i32mem:$src),
-              OpcodeStr#"\t{$src, $dst|$dst, $src}", []>,
+              OpcodeStr#"\t{$src, $dst|$dst, $src}", [], IIC_MPX>,
               Requires<[HasMPX, Not64BitMode]>;
   def 64rm: RI<opc, MRMSrcMem, (outs BNDR:$dst), (ins i64mem:$src),
-              OpcodeStr#"\t{$src, $dst|$dst, $src}", []>,
+              OpcodeStr#"\t{$src, $dst|$dst, $src}", [], IIC_MPX>,
               Requires<[HasMPX, In64BitMode]>;
 }
 }
@@ -29,17 +32,17 @@ defm BNDMK : mpx_bound_make<0x1B, "bndmk">, XS;
 multiclass mpx_bound_check<bits<8> opc, string OpcodeStr> {
 let mayLoad = 1 in {
   def 32rm: I<opc, MRMSrcMem, (outs), (ins  BNDR:$src1, i32mem:$src2),
-              OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
+              OpcodeStr#"\t{$src2, $src1|$src1, $src2}", [], IIC_MPX>,
               Requires<[HasMPX, Not64BitMode]>;
   def 64rm: RI<opc, MRMSrcMem, (outs), (ins  BNDR:$src1, i64mem:$src2),
-              OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
+              OpcodeStr#"\t{$src2, $src1|$src1, $src2}", [], IIC_MPX>,
               Requires<[HasMPX, In64BitMode]>;
 }
   def 32rr: I<opc, MRMSrcReg, (outs), (ins  BNDR:$src1, GR32:$src2),
-              OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
+              OpcodeStr#"\t{$src2, $src1|$src1, $src2}", [], IIC_MPX>,
               Requires<[HasMPX, Not64BitMode]>;
   def 64rr: RI<opc, MRMSrcReg, (outs), (ins  BNDR:$src1, GR64:$src2),
-              OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
+              OpcodeStr#"\t{$src2, $src1|$src1, $src2}", [], IIC_MPX>,
               Requires<[HasMPX, In64BitMode]>;
 }
 defm BNDCL : mpx_bound_check<0x1A, "bndcl">, XS;
@@ -47,32 +50,33 @@ defm BNDCU : mpx_bound_check<0x1A, "bndcu">, XD;
 defm BNDCN : mpx_bound_check<0x1B, "bndcn">, XD;
 
 def BNDMOVRMrr   : I<0x1A, MRMSrcReg, (outs BNDR:$dst), (ins BNDR:$src),
-                    "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
+                    "bndmov\t{$src, $dst|$dst, $src}", [], IIC_MPX>, PD,
                     Requires<[HasMPX]>;
 let mayLoad = 1 in {
 def BNDMOVRM32rm : I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i64mem:$src),
-                    "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
+                    "bndmov\t{$src, $dst|$dst, $src}", [], IIC_MPX>, PD,
                     Requires<[HasMPX, Not64BitMode]>;
 def BNDMOVRM64rm : RI<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i128mem:$src),
-                    "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
+                    "bndmov\t{$src, $dst|$dst, $src}", [], IIC_MPX>, PD,
                     Requires<[HasMPX, In64BitMode]>;
 }
 def BNDMOVMRrr   : I<0x1B, MRMDestReg, (outs BNDR:$dst), (ins BNDR:$src),
-                    "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
+                    "bndmov\t{$src, $dst|$dst, $src}", [], IIC_MPX>, PD,
                     Requires<[HasMPX]>;
 let mayStore = 1 in {
 def BNDMOVMR32mr : I<0x1B, MRMDestMem, (outs), (ins i64mem:$dst, BNDR:$src),
-                    "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
+                    "bndmov\t{$src, $dst|$dst, $src}", [], IIC_MPX>, PD,
                     Requires<[HasMPX, Not64BitMode]>;
 def BNDMOVMR64mr : RI<0x1B, MRMDestMem, (outs), (ins i128mem:$dst, BNDR:$src),
-                    "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
+                    "bndmov\t{$src, $dst|$dst, $src}", [], IIC_MPX>, PD,
                     Requires<[HasMPX, In64BitMode]>;
 
 def BNDSTXmr:      I<0x1B, MRMDestMem, (outs), (ins i64mem:$dst, BNDR:$src),
-                    "bndstx\t{$src, $dst|$dst, $src}", []>, PS,
+                    "bndstx\t{$src, $dst|$dst, $src}", [], IIC_MPX>, PS,
                     Requires<[HasMPX]>;
 }
 let mayLoad = 1 in
 def BNDLDXrm:      I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i64mem:$src),
-                    "bndldx\t{$src, $dst|$dst, $src}", []>, PS,
+                    "bndldx\t{$src, $dst|$dst, $src}", [], IIC_MPX>, PS,
                     Requires<[HasMPX]>;
+} // SchedRW
diff --git a/llvm/lib/Target/X86/X86Schedule.td b/llvm/lib/Target/X86/X86Schedule.td
index ffe4ca93fbd..ae22850408c 100644
--- a/llvm/lib/Target/X86/X86Schedule.td
+++ b/llvm/lib/Target/X86/X86Schedule.td
@@ -499,6 +499,7 @@ def IIC_IRET : InstrItinClass;
 def IIC_HLT : InstrItinClass;
 def IIC_LXS : InstrItinClass;
 def IIC_LTR : InstrItinClass;
+def IIC_MPX : InstrItinClass;
 def IIC_PKU : InstrItinClass;
 def IIC_PTWRITE : InstrItinClass;
 def IIC_RDPID : InstrItinClass;