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| author | Nadav Rotem <nadav.rotem@intel.com> | 2012-04-15 19:36:44 +0000 |
|---|---|---|
| committer | Nadav Rotem <nadav.rotem@intel.com> | 2012-04-15 19:36:44 +0000 |
| commit | 42bcd04ee3e55c694f10db115a769fd6295c067a (patch) | |
| tree | b6498944851e370ca18c7976c64278adc318076d | |
| parent | 5a833d66803eacf4f72da1b53b228ca0bd97ea7e (diff) | |
| download | bcm5719-llvm-42bcd04ee3e55c694f10db115a769fd6295c067a.tar.gz bcm5719-llvm-42bcd04ee3e55c694f10db115a769fd6295c067a.zip | |
Fix PR12529. The Vxx family of instructions are only supported by AVX.
Use non-vex instructions for SSE4.
llvm-svn: 154770
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSSE.td | 16 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/vec_shuffle-20.ll | 2 |
2 files changed, 14 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index 8210965d4ad..b0aeb3f5249 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -6742,6 +6742,16 @@ let Predicates = [HasAVX] in { def : Pat<(v4f64 (X86Blendpd (v4f64 VR256:$src1), (v4f64 VR256:$src2), (imm:$mask))), (VBLENDPDYrri VR256:$src2, VR256:$src1, imm:$mask)>; + + def : Pat<(v8i16 (X86Blendpw (v8i16 VR128:$src1), (v8i16 VR128:$src2), + (imm:$mask))), + (VPBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>; + def : Pat<(v4f32 (X86Blendps (v4f32 VR128:$src1), (v4f32 VR128:$src2), + (imm:$mask))), + (VBLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>; + def : Pat<(v2f64 (X86Blendpd (v2f64 VR128:$src1), (v2f64 VR128:$src2), + (imm:$mask))), + (VBLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>; } let Predicates = [HasAVX2] in { @@ -6802,13 +6812,13 @@ let Predicates = [HasSSE41] in { def : Pat<(v8i16 (X86Blendpw (v8i16 VR128:$src1), (v8i16 VR128:$src2), (imm:$mask))), - (VPBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>; + (PBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>; def : Pat<(v4f32 (X86Blendps (v4f32 VR128:$src1), (v4f32 VR128:$src2), (imm:$mask))), - (VBLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>; + (BLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>; def : Pat<(v2f64 (X86Blendpd (v2f64 VR128:$src1), (v2f64 VR128:$src2), (imm:$mask))), - (VBLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>; + (BLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>; } diff --git a/llvm/test/CodeGen/X86/vec_shuffle-20.ll b/llvm/test/CodeGen/X86/vec_shuffle-20.ll index b6b8ba6f846..976cd1835b4 100644 --- a/llvm/test/CodeGen/X86/vec_shuffle-20.ll +++ b/llvm/test/CodeGen/X86/vec_shuffle-20.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -o /dev/null -march=x86 -mcpu=corei7 -mtriple=i686-apple-darwin9 -stats -info-output-file - | grep asm-printer | grep 2 +; RUN: llc < %s -o /dev/null -march=x86 -mcpu=corei7 -mtriple=i686-apple-darwin9 -stats -info-output-file - | grep asm-printer | grep 3 define <4 x float> @func(<4 x float> %fp0, <4 x float> %fp1) nounwind { entry: |
