Clarify the doxygen comment for AsmPrinter::EmitDwarfRegOpPiece and add

default arguments to the function.

No functional change.

llvm-svn: 207372

2 files changed, 16 insertions, 9 deletions

diff --git a/llvm/include/llvm/CodeGen/AsmPrinter.h b/llvm/include/llvm/CodeGen/AsmPrinter.h
index f40f3337c7b..51eeb0fb77c 100644
--- a/llvm/include/llvm/CodeGen/AsmPrinter.h
+++ b/llvm/include/llvm/CodeGen/AsmPrinter.h
@@ -430,14 +430,21 @@ namespace llvm {
     /// encoding specified.
     virtual unsigned getISAEncoding() { return 0; }
 
-    /// \brief Emit a partial dwarf register operation.
+    /// \brief Emit a partial DWARF register operation.
     /// \param MLoc             the register
     /// \param PieceSizeInBits  size and
     /// \param PieceOffsetBits  offset of the piece in bits, if this is one
     ///                         piece of an aggregate value.
+    ///
+    /// If size and offset is zero an operation for the entire
+    /// register is emitted: Some targets do not provide a DWARF
+    /// register number for every register.  If this is the case, this
+    /// function will attempt to emit a DWARF register by emitting a
+    /// piece of a super-register or by piecing together multiple
+    /// subregisters that alias the register.
     void EmitDwarfRegOpPiece(ByteStreamer &BS, const MachineLocation &MLoc,
-                             unsigned PieceSize,
-                             unsigned PieceOffset) const;
+                             unsigned PieceSize = 0,
+                             unsigned PieceOffset = 0) const;
 
     /// EmitDwarfRegOp - Emit dwarf register operation.
     /// \param Indirect   whether this is a register-indirect address
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp
index 66606caa73d..02cd12be045 100644
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp
@@ -240,15 +240,15 @@ static void emitDwarfOpShr(ByteStreamer &Streamer,
   Streamer.EmitInt8(dwarf::DW_OP_shr, "DW_OP_shr");
 }
 
-/// Some targets do not provide a DWARF register number for every
-/// register.  This function attempts to emit a DWARF register by
-/// emitting a piece of a super-register or by piecing together
-/// multiple subregisters that alias the register.
+// Some targets do not provide a DWARF register number for every
+// register.  This function attempts to emit a DWARF register by
+// emitting a piece of a super-register or by piecing together
+// multiple subregisters that alias the register.
 void AsmPrinter::EmitDwarfRegOpPiece(ByteStreamer &Streamer,
                                      const MachineLocation &MLoc,
                                      unsigned PieceSizeInBits,
                                      unsigned PieceOffsetInBits) const {
-  assert(!MLoc.isIndirect());
+  assert(MLoc.isReg() && "MLoc must be a register");
   const TargetRegisterInfo *TRI = TM.getRegisterInfo();
   int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false);
 
@@ -346,7 +346,7 @@ void AsmPrinter::EmitDwarfRegOp(ByteStreamer &Streamer,
     }
 
     // Attempt to find a valid super- or sub-register.
-    return EmitDwarfRegOpPiece(Streamer, MLoc, 0, 0);
+    return EmitDwarfRegOpPiece(Streamer, MLoc);
   }
 
   if (MLoc.isIndirect())