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| author | Simon Tatham <simon.tatham@arm.com> | 2019-06-10 15:41:58 +0000 |
|---|---|---|
| committer | Simon Tatham <simon.tatham@arm.com> | 2019-06-10 15:41:58 +0000 |
| commit | 42078d41d59269d4d42873cf3260b58d09d530f0 (patch) | |
| tree | f644b7735e4d6c699c108ae548604a5157ca2d70 | |
| parent | 9650c95b7e55791faca4800c8f14f8325942a3b7 (diff) | |
| download | bcm5719-llvm-42078d41d59269d4d42873cf3260b58d09d530f0.tar.gz bcm5719-llvm-42078d41d59269d4d42873cf3260b58d09d530f0.zip | |
[ARM] Add the non-MVE instructions in Arm v8.1-M.
This should have been part of r362953, but I had a finger-trouble
incident and committed the old rather than new version of the patch.
Sorry.
llvm-svn: 362955
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrThumb2.td | 24 | ||||
| -rw-r--r-- | llvm/test/MC/ARM/thumbv8.1m.s | 16 |
2 files changed, 23 insertions, 17 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td index d8c6d3e625e..e324dbe5466 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -5167,8 +5167,7 @@ def t2LE : t2LOL<(outs ), (ins lelabel_u11:$label), "le", "$label"> { let Inst{10-1} = label{10-1}; } -let Uses = [CPSR] in { -class CS<string iname, list<dag> pattern=[]> +class CS<string iname, bits<4> opcode, list<dag> pattern=[]> : V8_1MI<(outs rGPR:$Rd), (ins GPRwithZR:$Rn, GPRwithZR:$Rm, pred_noal:$fcond), AddrModeNone, NoItinerary, iname, "$Rd, $Rn, $Rm, $fcond", "", pattern> { bits<4> Rd; @@ -5178,27 +5177,18 @@ class CS<string iname, list<dag> pattern=[]> let Inst{31-20} = 0b111010100101; let Inst{19-16} = Rn{3-0}; + let Inst{15-12} = opcode; let Inst{11-8} = Rd{3-0}; let Inst{7-4} = fcond{3-0}; let Inst{3-0} = Rm{3-0}; -} -} -def t2CSEL : CS<"csel"> { - let Inst{15-12} = 0b1000; + let Uses = [CPSR]; } -def t2CSINC : CS<"csinc"> { - let Inst{15-12} = 0b1001; -} - -def t2CSINV : CS<"csinv"> { - let Inst{15-12} = 0b1010; -} - -def t2CSNEG : CS<"csneg"> { - let Inst{15-12} = 0b1011; -} +def t2CSEL : CS<"csel", 0b1000>; +def t2CSINC : CS<"csinc", 0b1001>; +def t2CSINV : CS<"csinv", 0b1010>; +def t2CSNEG : CS<"csneg", 0b1011>; // CS aliases. diff --git a/llvm/test/MC/ARM/thumbv8.1m.s b/llvm/test/MC/ARM/thumbv8.1m.s index 9f0fcaea18b..9bb89c71204 100644 --- a/llvm/test/MC/ARM/thumbv8.1m.s +++ b/llvm/test/MC/ARM/thumbv8.1m.s @@ -1096,3 +1096,19 @@ csinv lr, r2, r2, mi # CHECK-FP: csel r0, r0, r1, eq @ encoding: [0x50,0xea,0x01,0x80] # CHECK-NOLOB: csel r0, r0, r1, eq @ encoding: [0x50,0xea,0x01,0x80] csel r0, r0, r1, eq + +// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: instructions in IT block must be predicable +it eq +csel r0, r0, r1, eq + +// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: instructions in IT block must be predicable +it eq +csinc r0, r0, r1, ne + +// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: instructions in IT block must be predicable +it gt +csinv r0, r0, r1, ge + +// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: instructions in IT block must be predicable +it lt +csneg r0, r0, r1, gt |
