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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-03-02 02:19:16 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-03-02 02:19:16 +0000 |
| commit | 41d2e3d98ec233b4c7f76931a2685897a98f8e23 (patch) | |
| tree | b91199fdb1954bed454d3c4b3f674af4f59190eb | |
| parent | b23041ad4d3a5a045fad0be10e6aa15db135f91a (diff) | |
| download | bcm5719-llvm-41d2e3d98ec233b4c7f76931a2685897a98f8e23.tar.gz bcm5719-llvm-41d2e3d98ec233b4c7f76931a2685897a98f8e23.zip | |
AMDGPU/GlobalISel: Define instruction mapping for G_FPTOSI
Patch by Tom Stellard
llvm-svn: 326534
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir | 31 |
2 files changed, 32 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index 958d1137f5b..8236242f900 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -293,6 +293,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { // Fall-through case AMDGPU::G_FADD: + case AMDGPU::G_FPTOSI: case AMDGPU::G_FPTOUI: case AMDGPU::G_FMUL: return getDefaultMappingVOP(MI); diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir new file mode 100644 index 00000000000..594cf9c6008 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir @@ -0,0 +1,31 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s +# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s + +--- +name: fptosi_s +legalized: true + +body: | + bb.0: + liveins: $sgpr0 + ; CHECK-LABEL: name: fptosi_s + ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; CHECK: [[FPTOSI:%[0-9]+]]:vgpr(s32) = G_FPTOSI [[COPY]](s32) + %0:_(s32) = COPY $sgpr0 + %1:_(s32) = G_FPTOSI %0 +... + +--- +name: fptosi_v +legalized: true + +body: | + bb.0: + liveins: $vgpr0 + ; CHECK-LABEL: name: fptosi_v + ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK: [[FPTOSI:%[0-9]+]]:vgpr(s32) = G_FPTOSI [[COPY]](s32) + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = G_FPTOSI %0 +... |
