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| author | Evan Cheng <evan.cheng@apple.com> | 2010-10-09 01:26:12 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-10-09 01:26:12 +0000 |
| commit | 4187f4942ef0569d77704379d964533652d477bc (patch) | |
| tree | 656eb2eb078561f4cb5dc29055daf0591c82bcf2 | |
| parent | 1c7fa43e6f66569b86a0402611fdcb7ad50c8331 (diff) | |
| download | bcm5719-llvm-4187f4942ef0569d77704379d964533652d477bc.tar.gz bcm5719-llvm-4187f4942ef0569d77704379d964533652d477bc.zip | |
Complete vld2 instruction itineries.
llvm-svn: 116136
| -rw-r--r-- | llvm/lib/Target/ARM/ARMScheduleA8.td | 37 |
1 files changed, 34 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/ARMScheduleA8.td b/llvm/lib/Target/ARM/ARMScheduleA8.td index 7aa03c4b4b9..e7118398451 100644 --- a/llvm/lib/Target/ARM/ARMScheduleA8.td +++ b/llvm/lib/Target/ARM/ARMScheduleA8.td @@ -412,7 +412,7 @@ def CortexA8Itineraries : ProcessorItineraries< // // VLD1u InstrItinData<IIC_VLD1u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<1, [A8_NLSPipe]>, + InstrStage<1, [A8_NLSPipe], 1>, InstrStage<1, [A8_LSPipe]>], [2, 2, 1]>, // @@ -436,8 +436,39 @@ def CortexA8Itineraries : ProcessorItineraries< // // VLD2 InstrItinData<IIC_VLD2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<1, [A8_NLSPipe]>, - InstrStage<1, [A8_LSPipe]>], [2, 2, 1]>, + InstrStage<1, [A8_NLSPipe], 1>, + InstrStage<1, [A8_LSPipe]>], + [2, 2, 1]>, + // + // VLD2x2 + InstrItinData<IIC_VLD2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrStage<3, [A8_NLSPipe], 1>, + InstrStage<3, [A8_LSPipe]>], + [2, 2, 3, 3, 1]>, + // + // VLD2ln + InstrItinData<IIC_VLD2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrStage<3, [A8_NLSPipe], 1>, + InstrStage<3, [A8_LSPipe]>], + [3, 3, 1, 1, 1, 1]>, + // + // VLD2u + InstrItinData<IIC_VLD2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrStage<1, [A8_NLSPipe], 1>, + InstrStage<1, [A8_LSPipe]>], + [2, 2, 2, 1, 1, 1]>, + // + // VLD2x2u + InstrItinData<IIC_VLD2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrStage<3, [A8_NLSPipe], 1>, + InstrStage<3, [A8_LSPipe]>], + [2, 2, 3, 3, 2, 1]>, + // + // VLD2lnu + InstrItinData<IIC_VLD2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrStage<3, [A8_NLSPipe], 1>, + InstrStage<3, [A8_LSPipe]>], + [3, 3, 2, 1, 1, 1, 1, 1]>, // // VLD3 InstrItinData<IIC_VLD3, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, |
