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authorChris Lattner <sabre@nondot.org>2005-10-02 06:23:51 +0000
committerChris Lattner <sabre@nondot.org>2005-10-02 06:23:51 +0000
commit4155ae0f7404644dfb32c883623f55ff0ca26e0c (patch)
tree4b1b25d9eddcc94dad983803ae910d4d4a85bb1b
parentd4ff3c13245361eaf02dc63a6954ef75778ebcfa (diff)
downloadbcm5719-llvm-4155ae0f7404644dfb32c883623f55ff0ca26e0c.tar.gz
bcm5719-llvm-4155ae0f7404644dfb32c883623f55ff0ca26e0c.zip
Adjust to change in ctor
llvm-svn: 23585
-rw-r--r--llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp10
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp b/llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp
index 6149ad62624..d2d0946053f 100644
--- a/llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp
+++ b/llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp
@@ -43,7 +43,7 @@ namespace {
SparcV9::g7, SparcV9::o6
};
struct IRClass : public TargetRegisterClass {
- IRClass() : TargetRegisterClass(8, 8, IR, IR + 32) {}
+ IRClass() : TargetRegisterClass(MVT::i64, 8, 8, IR, IR + 32) {}
} IRInstance;
@@ -71,7 +71,7 @@ namespace {
// one (32, 34, ...), and they must contain double-fp or quad-fp
// values... see below about the aliasing problems.
struct FRClass : public TargetRegisterClass {
- FRClass() : TargetRegisterClass(4, 8, FR, FR + 64) {}
+ FRClass() : TargetRegisterClass(MVT::f32, 4, 8, FR, FR + 64) {}
} FRInstance;
@@ -80,7 +80,7 @@ namespace {
SparcV9::xcc, SparcV9::icc, SparcV9::ccr
};
struct ICCRClass : public TargetRegisterClass {
- ICCRClass() : TargetRegisterClass(1, 8, ICCR, ICCR + 3) {}
+ ICCRClass() : TargetRegisterClass(MVT::i1, 1, 8, ICCR, ICCR + 3) {}
} ICCRInstance;
@@ -89,7 +89,7 @@ namespace {
SparcV9::fcc0, SparcV9::fcc1, SparcV9::fcc2, SparcV9::fcc3
};
struct FCCRClass : public TargetRegisterClass {
- FCCRClass() : TargetRegisterClass(1, 8, FCCR, FCCR + 4) {}
+ FCCRClass() : TargetRegisterClass(MVT::i1, 1, 8, FCCR, FCCR + 4) {}
} FCCRInstance;
@@ -98,7 +98,7 @@ namespace {
SparcV9::fsr
};
struct SRClass : public TargetRegisterClass {
- SRClass() : TargetRegisterClass(8, 8, SR, SR + 1) {}
+ SRClass() : TargetRegisterClass(MVT::i64, 8, 8, SR, SR + 1) {}
} SRInstance;
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