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author | Chad Rosier <mcrosier@apple.com> | 2011-12-21 19:14:52 +0000 |
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committer | Chad Rosier <mcrosier@apple.com> | 2011-12-21 19:14:52 +0000 |
commit | 3ede414127de950af70a033c152eb5901a390f53 (patch) | |
tree | e08fdc3da3c6f3b457369c7c86d85a962c004086 | |
parent | 7248bda595ab844c748da806b5bedcab8d571c15 (diff) | |
download | bcm5719-llvm-3ede414127de950af70a033c152eb5901a390f53.tar.gz bcm5719-llvm-3ede414127de950af70a033c152eb5901a390f53.zip |
No case stmt for BUILD_VECTOR in PerformDAGCombine(), so I assume this isn't
necessary. Please chime in if I'm mistaken.
llvm-svn: 147065
-rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 95c99e1dc27..d8481b80919 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -1190,7 +1190,6 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) // We have target-specific dag combine patterns for the following nodes: setTargetDAGCombine(ISD::VECTOR_SHUFFLE); setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); - setTargetDAGCombine(ISD::BUILD_VECTOR); setTargetDAGCombine(ISD::VSELECT); setTargetDAGCombine(ISD::SELECT); setTargetDAGCombine(ISD::SHL); |