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| author | Renato Golin <renato.golin@linaro.org> | 2016-03-03 08:57:44 +0000 |
|---|---|---|
| committer | Renato Golin <renato.golin@linaro.org> | 2016-03-03 08:57:44 +0000 |
| commit | 3d78271eacf88f9ceed2bab446942077c868aeb5 (patch) | |
| tree | b4da5a0d3986d43a75f0057a9d630e3631216463 | |
| parent | abbe34bce65b74ad23b4304eb180691d8685f6a0 (diff) | |
| download | bcm5719-llvm-3d78271eacf88f9ceed2bab446942077c868aeb5.tar.gz bcm5719-llvm-3d78271eacf88f9ceed2bab446942077c868aeb5.zip | |
Revert "[ARM] Merging 64-bit divmod lib calls into one"
This reverts commit r262507, which broke some ARM buildbots.
llvm-svn: 262594
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 9 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/divmod-eabi.ll | 4 |
3 files changed, 2 insertions, 14 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index a81cb664584..216389ac42a 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -2153,9 +2153,8 @@ SDValue DAGCombiner::useDivRem(SDNode *Node) { if (Node->use_empty()) return SDValue(); // This is a dead node, leave it alone. - // DivMod lib calls can still work on non-legal types if using lib-calls. EVT VT = Node->getValueType(0); - if (VT.isVector() || !VT.isInteger()) + if (!TLI.isTypeLegal(VT)) return SDValue(); unsigned Opcode = Node->getOpcode(); diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index a0bf9179427..479b6d29be9 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -809,8 +809,6 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM, setOperationAction(ISD::SDIVREM, MVT::i32, Custom); setOperationAction(ISD::UDIVREM, MVT::i32, Custom); - setOperationAction(ISD::SDIVREM, MVT::i64, Custom); - setOperationAction(ISD::UDIVREM, MVT::i64, Custom); } else { setOperationAction(ISD::SDIVREM, MVT::i32, Expand); setOperationAction(ISD::UDIVREM, MVT::i32, Expand); @@ -7056,13 +7054,6 @@ void ARMTargetLowering::ReplaceNodeResults(SDNode *N, case ISD::UREM: Res = LowerREM(N, DAG); break; - case ISD::SDIVREM: - case ISD::UDIVREM: - Res = LowerDivRem(SDValue(N, 0), DAG); - assert(Res.getNumOperands() == 2 && "DivRem needs two values"); - Results.push_back(Res.getValue(0)); - Results.push_back(Res.getValue(1)); - return; case ISD::READCYCLECOUNTER: ReplaceREADCYCLECOUNTER(N, Results, DAG, Subtarget); return; diff --git a/llvm/test/CodeGen/ARM/divmod-eabi.ll b/llvm/test/CodeGen/ARM/divmod-eabi.ll index 29c7fe0ff86..35f2014317b 100644 --- a/llvm/test/CodeGen/ARM/divmod-eabi.ll +++ b/llvm/test/CodeGen/ARM/divmod-eabi.ll @@ -79,6 +79,7 @@ entry: ret i32 %add2 } +; FIXME: AEABI is not lowering long u/srem into u/ldivmod define i64 @longf(i64 %a, i64 %b) { ; EABI-LABEL: longf: ; DARWIN-LABEL: longf: @@ -86,9 +87,6 @@ entry: %div = sdiv i64 %a, %b %rem = srem i64 %a, %b ; EABI: __aeabi_ldivmod -; EABI-NEXT: adds r0 -; EABI-NEXT: adc r1 -; EABI-NOT: __aeabi_ldivmod ; DARWIN: ___divdi3 ; DARWIN: mov [[div1:r[0-9]+]], r0 ; DARWIN: mov [[div2:r[0-9]+]], r1 |
