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| author | Alex Bradbury <asb@lowrisc.org> | 2017-10-19 16:22:51 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2017-10-19 16:22:51 +0000 |
| commit | 3c941e7ed92a5043d6e09b9885a0c66b52f7882e (patch) | |
| tree | 26e3d09410a6665a45536d042ee5069afb448b2e | |
| parent | baa54d4ac868a31ce5e33274dc80cf5106e7908e (diff) | |
| download | bcm5719-llvm-3c941e7ed92a5043d6e09b9885a0c66b52f7882e.tar.gz bcm5719-llvm-3c941e7ed92a5043d6e09b9885a0c66b52f7882e.zip | |
[RISCV] RISCVAsmParser: early exit if RISCVOperand isn't immediate as expected
This is necessary to avoid an assertion in the included test case and similar
assembler inputs.
llvm-svn: 316168
| -rw-r--r-- | llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 10 | ||||
| -rw-r--r-- | llvm/test/MC/RISCV/rv32i-invalid.s | 3 |
2 files changed, 13 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index 92acdd825d5..486784859bd 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -146,6 +146,8 @@ public: template <int N> bool isBareSimmNLsb0() const { int64_t Imm; RISCVMCExpr::VariantKind VK; + if (!isImm()) + return false; bool IsConstantImm = evaluateConstantImm(Imm, VK); bool IsValid; if (!IsConstantImm) @@ -185,6 +187,8 @@ public: bool isUImm5() const { int64_t Imm; RISCVMCExpr::VariantKind VK; + if (!isImm()) + return false; bool IsConstantImm = evaluateConstantImm(Imm, VK); return IsConstantImm && isUInt<5>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; } @@ -193,6 +197,8 @@ public: RISCVMCExpr::VariantKind VK; int64_t Imm; bool IsValid; + if (!isImm()) + return false; bool IsConstantImm = evaluateConstantImm(Imm, VK); if (!IsConstantImm) IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK, Imm); @@ -205,6 +211,8 @@ public: bool isUImm12() const { int64_t Imm; RISCVMCExpr::VariantKind VK; + if (!isImm()) + return false; bool IsConstantImm = evaluateConstantImm(Imm, VK); return IsConstantImm && isUInt<12>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; } @@ -215,6 +223,8 @@ public: RISCVMCExpr::VariantKind VK; int64_t Imm; bool IsValid; + if (!isImm()) + return false; bool IsConstantImm = evaluateConstantImm(Imm, VK); if (!IsConstantImm) IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK, Imm); diff --git a/llvm/test/MC/RISCV/rv32i-invalid.s b/llvm/test/MC/RISCV/rv32i-invalid.s index da49b93bb62..3e4ac85ed60 100644 --- a/llvm/test/MC/RISCV/rv32i-invalid.s +++ b/llvm/test/MC/RISCV/rv32i-invalid.s @@ -122,6 +122,9 @@ sub t0, t2, 1 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction add ra, zero, zero, zero # CHECK: :[[@LINE]]:21: error: invalid operand for instruction sltiu s2, s3, 0x50, 0x60 # CHECK: :[[@LINE]]:21: error: invalid operand for instruction +# Memory operand not formatted correctly +lw a4, a5, 111 # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the range [-2048, 2047] + # Too few operands ori a0, a1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction xor s2, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction |
