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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-01-12 18:08:41 -0500 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2020-01-12 22:44:51 -0500 |
| commit | 3c868cbbda7e2ff66b8ed92b632a609aaac324ba (patch) | |
| tree | e150735e5d9d4be0dbea0f98e62b54e9b8970d10 | |
| parent | 555e7ee04cb5c44e0b11a2eda999e6910b4b27e1 (diff) | |
| download | bcm5719-llvm-3c868cbbda7e2ff66b8ed92b632a609aaac324ba.tar.gz bcm5719-llvm-3c868cbbda7e2ff66b8ed92b632a609aaac324ba.zip | |
AMDGPU: Split test function
This avoids slightly different scheduling/regalloc behavior, and
avoids a test diff between GlobalISel and SelectionDAG.
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/write_register.ll | 20 |
1 files changed, 16 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/write_register.ll b/llvm/test/CodeGen/AMDGPU/write_register.ll index 0ca92f90c22..eb9b103775a 100644 --- a/llvm/test/CodeGen/AMDGPU/write_register.ll +++ b/llvm/test/CodeGen/AMDGPU/write_register.ll @@ -24,13 +24,25 @@ define amdgpu_kernel void @test_write_exec(i64 %val) #0 { ret void } -; CHECK-LABEL: {{^}}test_write_flat_scratch: +; CHECK-LABEL: {{^}}test_write_flat_scratch_0: ; CHECK: s_mov_b64 flat_scratch, 0 -; CHECK: s_mov_b64 flat_scratch, -1 -; CHECK: s_mov_b64 flat_scratch, s{{\[[0-9]+:[0-9]+\]}} -define amdgpu_kernel void @test_write_flat_scratch(i64 %val) #0 { +define amdgpu_kernel void @test_write_flat_scratch_0(i64 %val) #0 { call void @llvm.write_register.i64(metadata !2, i64 0) + call void @llvm.amdgcn.wave.barrier() #1 + ret void +} + +; CHECK-LABEL: {{^}}test_write_flat_scratch_neg1: +; CHECK: s_mov_b64 flat_scratch, -1 +define amdgpu_kernel void @test_write_flat_scratch_neg1(i64 %val) #0 { call void @llvm.write_register.i64(metadata !2, i64 -1) + call void @llvm.amdgcn.wave.barrier() #1 + ret void +} + +; CHECK-LABEL: {{^}}test_write_flat_scratch_val: +; CHECK: s_load_dwordx2 flat_scratch, s{{\[[0-9]+:[0-9]+\]}} +define amdgpu_kernel void @test_write_flat_scratch_val(i64 %val) #0 { call void @llvm.write_register.i64(metadata !2, i64 %val) call void @llvm.amdgcn.wave.barrier() #1 ret void |
