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| author | Johnny Chen <johnny.chen@apple.com> | 2011-04-12 23:31:00 +0000 |
|---|---|---|
| committer | Johnny Chen <johnny.chen@apple.com> | 2011-04-12 23:31:00 +0000 |
| commit | 3c2f74c9f30013ae5885f3e0a80798cf5ea6d253 (patch) | |
| tree | a7b085501139839dd39d7c23d5e6df24ebb5e5d6 | |
| parent | 9c8cd4c0978d59f53f6f3e42e478e6aa2985e346 (diff) | |
| download | bcm5719-llvm-3c2f74c9f30013ae5885f3e0a80798cf5ea6d253.tar.gz bcm5719-llvm-3c2f74c9f30013ae5885f3e0a80798cf5ea6d253.zip | |
Add sanity check for Ld/St Dual forms of Thumb2 instructions.
rdar://problem/9273947
llvm-svn: 129411
3 files changed, 52 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h b/llvm/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h index e29d84604ec..42d7a73bf5f 100644 --- a/llvm/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h +++ b/llvm/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h @@ -1275,6 +1275,35 @@ static bool DisassembleThumb2LdStDual(MCInst &MI, unsigned Opcode, && OpInfo[3].RegClass < 0 && "Expect >= 4 operands and first 3 as reg operands"); + // Thumnb allows for specifying Rt and Rt2, unlike ARM (which has Rt2==Rt+1). + unsigned Rt = decodeRd(insn); + unsigned Rt2 = decodeRs(insn); + unsigned Rn = decodeRn(insn); + + // Some sanity checking first. + + // A8.6.67 LDRD (literal) has its W bit as (0). + if (Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2LDRD_PRE || Opcode == ARM::t2LDRD_POST) { + if (Rn == 15 && slice(insn, 21, 21) != 0) + return false; + } else { + // For Dual Store, PC cannot be used as the base register. + if (Rn == 15) { + DEBUG(errs() << "if n == 15 then UNPREDICTABLE\n"); + return false; + } + } + if (Rt == Rt2) { + DEBUG(errs() << "if t == t2 then UNPREDICTABLE\n"); + return false; + } + if (Opcode != ARM::t2LDRDi8 && Opcode != ARM::t2STRDi8) { + if (Rn == Rt || Rn == Rt2) { + DEBUG(errs() << "if wback && (n == t || n == t2) then UNPREDICTABLE\n"); + return false; + } + } + // Add the <Rt> <Rt2> operands. unsigned RegClassPair = OpInfo[0].RegClass; unsigned RegClassBase = OpInfo[2].RegClass; diff --git a/llvm/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt b/llvm/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt new file mode 100644 index 00000000000..da2e6bed861 --- /dev/null +++ b/llvm/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt @@ -0,0 +1,13 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=1930 Name=t2LDRD_PRE Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 1: 0: 0: 1| 1: 1: 1: 1| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.66 LDRD (immediate) +# if Rn = '1111' then SEE LDRD (literal) +# A8.6.67 LDRD (literal) +# Inst{21} = 0 +0xff 0xe9 0x0 0xeb diff --git a/llvm/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt b/llvm/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt new file mode 100644 index 00000000000..c8f8ec294ec --- /dev/null +++ b/llvm/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=2124 Name=t2STRD_PRE Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 1: 0: 0: 1| 1: 1: 1: 0| 0: 1: 0: 0| 0: 1: 0: 0| 0: 1: 1: 0| 0: 0: 0: 0| 0: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# +# if wback && (n == t || n == t2) then UNPREDICTABLE +0xe4 0xe9 0x02 0x46 |
